SM34 Data Sheet #:

TM095

Page 26

Rev:

05 Date: 11/19/12

© Copyright 2012 The Connor-Winfield Corp. All Rights Reserved

Specifications subject to change without notice

Application Notes continued

Master/Slave Configuration – A pair of devices are interconnected by cross-coupling their respective Output1 to the other

device’s

M/S REF input (See Figure 8). Additionally, the reference inputs for each device would typically be correspondingly the same,

so that when a Master/Slave switch occurs, synchronization would continue with the same reference. The references may be driven by

the same signal directly or via separate drivers, as the redundancy of that part of the system requires. Distribution path lengths are not

critical here, as a phase build-out will occur when a device switches from slave to master.

To accommodate path length delays in slave mode, the SM3 provides a programmable phase skew feature, which allows the

application to offset the output clock from the cross-reference signal by -32ns to +31.75ns. This offset may therefore be programmed

to exactly compensate for the actual path length delay associated with the particular application’s cross-reference traces. The offset

may be further adjusted to accommodate any output clock distribution path delay differences. Phase offset is programmed by writing

to the Phase_Offset register, and is typically a one-time device initialization function. (See register description and Register Access

Control sections). Thus, master/slave switches with the SM3 devices may be accomplished with near-zero phase hits.

Master/Slave Operation and Control – Master or slave state of a device is determined by the MASTER SELECT pin. Choosing

the master/slave states is a function of the application, based on the configuration of the rest of the system and potential detected fault

conditions.

When operating in Hardware Control or Register Access Manual Control mode, it is important to set the slave reference selection

the same as the master to ensure use of the same reference when/if the slave becomes master. In Register Access Manual Control

mode, the

Ref_Mask register should also be written to the same value for both devices.

Master/slave switches should be performed with minimal delay between switching the states of each of the two devices. This can

be easily accomplished, for example, by controlling the master/slave state with a single signal, coupled to one of the devices through

an inverter.

In the case of Register Access Automatic Control mode, where reference selection is automatic, it is necessary to read the

operational mode BITS 3-0) from the master’s

Op_Mode register and write it to the slave’s Op_Mode register. The master’s reference

selection will then be used by the slave when it becomes master. In addition to having the references populated the same, and in the

same order for both devices, it is desirable to write the reference frequency and priority registers

Ref(1-4)_Frq_Priority and the Ref_

Mask registers to the same values for both devices to ensure seamless master/slave switches.

Reset – Device reset is an initialization time function, which resets internal logic and register values. A reset is performed

automatically when the device is powered up. Registers return to their default values, as noted in the register descriptions. Device

mode and functionality following a reset are determined by the state of the various hardware control pins.

Holdover History Accumulation and Maintenance – Holdover history accumulation and maintenance may be controlled in

greater detail if register bus access to the device is provided. Holdover history accumulation and control encompasses three device

internal registers, three bus access registers for control and access, and two status bits in the

DPLL_Status register.

Once lock has been achieved, holdover history is compiled in the accumulation register. It is transferred to the Active holdover history

when it is ready (typically in about 15 minutes). The “Holdover Available” bit and output pin are set to “1”. From then on, the Active

holdover history is continually updated and kept in sync with the holdover history accumulation register. (See Figure 9).

Hold Over History

Accumulation Register

Active

Hold Over History

Backup

Hold Over History

Holdover History Register

Figure 9