MT9V024 datasheet(49/62 Pages) ONSEMI

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MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Feature Description

LVDS Data Bus Timing

The LVDS bus timing waveforms and timing specifications are shown in Table 12 and

Figure 37.

Figure 37:

LVDS Timing

Table 12:

LVDS AC Timing Specifications

VPWR = 3.3V ±0.3V; TJ = – 40°C to +105°C; output load = 100 ; frequency 27 MHz

Parameter

Minimum

Typical

Maximum

Unit

LVDS clock rise time

–

0.22

0.30

LVDS clock fall time

–

0.22

0.30

LVDS data rise time

–

0.28

0.30

LVDS data fall time

–

0.28

0.30

LVDS data setup time

0.3

0.67

–

LVDS data hold time

0.1

1.34

–

LVDS clock jitter

–

Data Rise/Fall Time

(10% - 90%)

Data Setup Time

Data Hold Time

LVDS Data Output

(SER_DATAOUT_N/P)

LVDS Clock Output

(Shft_CLKOUT_N/P)

Clock Rise/Fall Time

(10% - 90%)

Clock Jitter

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