MT9V024 datasheet(33/62 Pages) ONSEMI

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MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Feature Description

For context A these become:

t1 = R0x08 + R0xD3

(EQ 11)

t2 = R0x09 - R0x08 + R0xD4 – R0xD3

(EQ 12)

t3 = R0x0B + R0xD4 – t1 – t2

(EQ 13)

For context B these are:

t1 = R0xCF + R0xD6

(EQ 14)

t2 = R0xD0 - R0xCF + R0xD7 - R0xD6

(EQ 15)

t3 = R0xD2 + R0xD8 -t1 -t2

(EQ 16)

In all cases above, the coarse component of total integration time may be based on the

result of AEC or values in R0x0B and R0xD2, depending on the settings.

Similar to Fine Shutter Width Total registers, the user must not set the Fine Shutter

Width 1 or Fine Shutter Width 2 register to exceed the row time (Horizontal Blanking +

Window Width). The absolute maximum value for the Fine Shutter Width registers is

1774 master clocks.

ADC Companding Mode

By default, ADC resolution of the sensor is 10-bit. Additionally, a companding scheme of

12-bit into 10-bit is enabled by the ADC Companding Mode register. This mode allows

higher ADC resolution, which means less quantization noise at low light, and lower reso-

lution at high light, where good ADC quantization is not so critical because of the high

level of the photon’s shot noise.

Figure 25:

12- to 10-Bit Companding Chart

256

512

768

1,024

4,096

2,048

1,024

512

256

4 to 1 Companding (512 - 2047

384 - 767)

8 to 1 Companding (2,048- 4095

768- 1023)

10-bit

Codes

12-bit

Codes

2 to 1 Companding (256- 511

256- 383)

No companding (0 -255

0 -255)

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