Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

SM8702AM Datasheet(PDF) 3 Page - Nippon Precision Circuits Inc

Part # SM8702AM
Description  Clock Generator IC
PDF  16 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NPC [Nippon Precision Circuits Inc]
Direct Link  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM8702AM Datasheet(HTML) 3 Page - Nippon Precision Circuits Inc

  SM8702AM Datasheet HTML 1Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 2Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 3Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 4Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 5Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 6Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 7Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 8Page - Nippon Precision Circuits Inc SM8702AM Datasheet HTML 9Page - Nippon Precision Circuits Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 3 / 16 page
background image
SM8702AM
NIPPON PRECISION CIRCUITS—3
BLOCK DIAGRAM
PIN DESCRIPTION
Number
Name
I/O
Function
Notes
1
VDD1
–
3.3V supply
X T, XTN oscillator, REF[0:1] buffer, stop logic, 3.3V line
2
REF0
I/O
14.318MHz reference clock output
3
V S S
–
Ground
Cr ystal oscillator, REF[0:1], 3.3Vline
4
X T
I
Cr ystal oscillator input
5
X T N
O
Cr ystal oscillator output
6
VDD2
–
3.3V supply
PCI clock output buffers, pre-buffer, stop logic, and
internal circuit logic supply
7
PCICLK_F
O
PCI bus free-running clock output
MODE
I
Mode settings (latch input)
CPU_ST OP# (pin 17) and PCI_STOP# (pin 18) mode
select pin.
MODE = HIGH: Desktop mode
MODE = LOW: Mobile mode
8
PCICLK0
O
PCI bus clock output
9
V S S
–
Ground (3.3V supply)
PCI clock output buffers, pre-buffer, stop logic
1 0
PCICLK1
O
PCI bus clock output
SS_CONTROLLER
DIV/3
to DIV/6
DIV/2
N-Countor
Phase
Detector
Charge
Pump
VCO
R-Countor
Unlock Detector
Current
Source
N-Countor
Phase
Detector
Charge
Pump
VCO
R-Countor
Unlock Detector
Current
Source
Buff. Amp.
I/O
Latch
Control Logic
DIV/3
1/2
ROM
XT
XTN
(1st PLL)
BUFFERIN
FS[0:2]
MODE
SDATA
SCLK
CPU_STOP#
PCI_STOP#
PCICLK_F
(MS)
PCICLK
[0:4]
IOAPIC
48MHz
(USB)
REF[0:1]
(2nd PLL)
CPUCLK
[0:1]
SDRAM
[0:13]
5
2
14
2
24MHz
(Super I/O)
3
I C
2



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com