L6362A datasheet(8/37 Pages) STMICROELECTRONICS

8 / 37 page

Pin description

L6362A

8/37

DocID027660 Rev 4

2.1

IN1, IN2

These pins control the output stage on OUTH and OUTL pins, see Table 14: "Output stage

truth table". When used in push-pull configuration (OUTH and OUTL wired together), the IC

must be driven by the IN2 pin, to allow the deadtime function to protect the output stage.

The IN1 pin can be wired to GND or VDD depending on the desired polarity. In order to

avoid IC overstress, in push-pull configuration, IN1 pin has to be hardwired to VDD or GND.

IN1 could be also actively controlled, but must be switched only while EN/DIAG pin is at a

low logic level. When used in high-side (OUTL left unconnected) or low-side (OUTH left

unconnected) configurations, the IC should be driven by the IN1 pin, in order to avoid the

unnecessary delay, which is introduced by the deadtime function. The pin IN2 can be wired

to GND or VDD depending on the desired polarity, or can be actively controlled (for example

by a microcontroller).

2.2

EN/DIAG

This pin controls the output stage on pins OUTH and OUTL. When EN/DIAG is at a low

logic level (GND), the output stage is disabled. The EN/DIAG pin is also internally wired to

an open drain transistor, used for diagnostic purposes and must be driven through a series

resistor. The open drain transistor turns on in case of faults. EN/DIAG pin has an internal

weak pull-down resistor. If the OUTH and OUTL pins are wired together the IC can be still

used in HS or LS mode (with slow demagnetization) by applying a fixed high or low level

voltage to IN1 pin, using the IN2 pin to set the polarity and the EN/DIAG pin to control the

power stage.

2.3

OUT I/Q

This pin reports the status of the receiver line (I/Q). It swings from GND to VDD and should

generally be connected to a microcontroller input. OUTI/Q relation to I/Q is shown in Table

14: "Output stage truth table" . It must be connected to ground if it is not used.

2.4

SEL

This pin cannot be left floating and it allows the linear regulator output voltage to be

configured at 3.3 V or 5 V.

Table 3: Linear regulator voltage configuration

SEL

VDD supplied voltage

GND

3.3 V

VDD

5 V

2.5

VDD

This is the output of the integrated linear voltage regulator and the supply voltage of the I/O

interface. It can supply a small current (Iscr) to a microcontroller or external circuitry. The

integrated liner regulator could supply the whole system, provided that the amount of

required current is within IC limits, or the system can be supplied by an external regulator

and the regulator integrated in the IC supplies the integrated logic only.

2.6

GND

IC ground.

L6362A Datasheet(PDF) 8 Page - STMicroelectronics

L6362A Datasheet(HTML) 8 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

Datasheet Download

Link URL