ADS8331IBRGET datasheet(21/57 Pages) TI1

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ADS8331

ADS8332

COM

OPA211

MUXOUT

ADCIN

2.048VDC

600W

InputSignal

( 2Vto+2V)

20W

1000pF

600W

ADS8331, ADS8332

www.ti.com

SBAS363D – DECEMBER 2009 – REVISED OCTOBER 2015

Feature Description (continued)

8.3.2.2 Bipolar to Unipolar Driver

In systems where the input signal is bipolar, op amps such as the OPA365 and OPA211 can be used in the

inverting configuration with a DC bias applied to the noninverting input to keep the input signal to the ADS833x

within its rated operating voltage range. TI also recommends this configuration when the ADS833x is used in

signal-processing applications where good SNR and THD performance is required. The DC bias can be derived

from low-noise reference voltage ICs such as the REF5025 or REF5040. The input configuration shown in

Figure 36 is capable of delivering better than 91-dB SNR and –99-dB THD at an input frequency of 1 kHz. If

bandpass filters are used to filter the input to the driving operational amplifier, the signal swing at the input of the

bandpass filter should be small enough to minimize the distortion introduced by the filter. In these cases, the gain

of the circuit shown in Figure 36 can be increased to maintain a large enough input signal to the ADS833x to

keep the system SNR as high as possible.

Figure 36. Bipolar Input Drive Configuration

8.4 Device Functional Modes

8.4.1 Reference

The ADS833x can operate with an external reference with a range from 1.2 V to 4.2 V. A clean, low-noise

reference voltage on this pin is required to ensure good converter performance. A low-noise band-gap reference

such as the REF5025 or REF5040 can be used to drive this pin. A 10-

μF ceramic bypass capacitor is required

between the REF+ and REF– pins of the converter. This capacitor should be placed as close as possible to the

pins of the device. The REF– pin should not be connected to the AGND pin of the converter; instead, the REF–

pin must be connected to the analog ground plane with a separate via.

8.4.2 Converter Operation

The ADS833x has an internal oscillator that can be used as the conversion clock (CCLK) source. The minimum

frequency of this oscillator is 10.5 MHz. The internal oscillator is only active during the conversion period unless

the converter is using Auto-Trigger and/or Auto-NAP modes. The minimum acquisition/sampling time for the

ADS833x is 3 CCLKs (250 ns with a 12-MHz conversion clock), while the minimum conversion time is 18 CCLKs

(1500 ns with a 12-MHz conversion clock).

As shown in Figure 37, the ADS833x can also be programmed to run conversions using the external serial clock

(SCLK). This feature allows system designers to achieve system synchronization. Each rising edge of SCLK

toggles the state of the conversion clock (CCLK), which reduces the frequency of SCLK by a factor of two before

it is used as CCLK. For example, a 21-MHz SCLK provides a 10.5-MHz CCLK. If the start of a conversion must

occur on a specific rising edge of SCLK when the external serial clock is used for the conversion clock (and

Manual-Trigger mode is enabled), a minimum setup time of 20 ns between the falling edge of CONVST and the

rising edge of SCLK must be met. This timing ensures the conversion is completed in 18 CCLKs (36 SCLKs).

The duty cycle of SCLK is not critical, as long as the minimum high and low times (11 ns for VA = 5 V) are

satisfied. Because the ADS833x is designed for high-speed applications, a high-frequency serial clock must be

supplied to maintain the high throughput of the interface. This requirement can be accomplished if the period of

SCLK is at most 1

μs when SCLK is used as the conversion clock (CCLK). The 1-μs maximum period for SCLK

is also set by the leakage of charge from the capacitors in the capacitive digital-to-analog converter (CDAC)

block in the ADS833x. If SCLK is used as the conversion clock, the SCLK source must have minimal rise/fall

times and low jitter to provide the best converter performance.

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