ADS8331IBRGET datasheet(29/57 Pages) TI1

29 / 57 page

ADS8331, ADS8332

www.ti.com

SBAS363D – DECEMBER 2009 – REVISED OCTOBER 2015

Programming (continued)

NOTE

There are cases where a cycle can be anywhere from 4 SCLKs up to 24 SCLKs,

depending on the read mode combination. See Table 4 for details.

8.5.1.1 Internal Register

The internal register consists of two parts: four bits for the Command register (CMR) and 12 bits for the

Configuration register (CFR).

Table 4. Command Set Defined by Command Register (CMR)(1)

WAKE UP

MINIMUM

D[15:12]

HEX

COMMAND

D[11:0]

FROM AUTO-

SCLKs

R/W

NAP

REQUIRED

0000b

Select analog input channel 0

Don't care

0001b

Select analog input channel 1

Don't care

0010b

Select analog input channel 2

Don't care

0011b

Select analog input channel 3

Don't care

0100b

Select analog input channel 4(2)

Don't care

0101b

Select analog input channel 5(2)

Don't care

0110b

Select analog input channel 6(2)

Don't care

0111b

Select analog input channel 7(2)

Don't care

1000b

Reserved

—

1001b

Reserved

—

1010b

Reserved

—

1011b

Wake up

Don't care

1100b

Read CFR

Don't care

—

1101b

Read data

Don't care

—

1110b

Write CFR

CFR Value

—

Default mode

1111b

Don't care

(load CFR with default value)

(1)

The first four bits from SDO after the falling edge of FS/CS are the four MSBs from the previous conversion result. The next 12 bits from

SDO are the contents of the CFR.

(2)

These commands apply only to the ADS8332; they are reserved (not available) for the ADS8331.

Submit Documentation Feedback

Product Folder Links: ADS8331 ADS8332

ADS8331IBRGET Datasheet(PDF) 29 Page - Texas Instruments

ADS8331IBRGET Datasheet(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57

Datasheet Download

Link URL