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ADS8331IBRGET Datasheet(PDF) 33 Page - Texas Instruments

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Part # ADS8331IBRGET
Description  Low-Power, 16-Bit, 500-kSPS, 4-/8-Channel Unipolar Input Analog-to-Digital Converters
PDF  57 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS8331IBRGET Datasheet(HTML) 33 Page - Texas Instruments

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background image
CONVST
CONVST
CONVST
#1
#2
#3
EOC#1
(activelow)
CS #2
#3
CS
SCLK#1
SCLK#2
SCLK#3
SDO#1
CDI#2
SDO#2
CDI#3
Conversion N
1..............16
ManualTrigger,ReadWhileSampling
(UseinternalCCLK,EOCactivelow,andTAGmodedisabled)
High-Z
High-Z
CS #1
t
=18CCLK
CONV
t
=3CCLKmin
SAMPLE1
t
SU2
t
SU2
SDO#3
1..............16
1..............16
Conversion
fromDevice#1
N
SDI#1
SDI#2
SDI#3
Don'tCare
Configure
ReadData
ReadData
Don'tCare
t
WH1
t
WH1
t
WH1
t
WH1
Conversion
fromDevice#1
N
Conversion
fromDevice#1
N
High-Z
High-Z
Conversion
fromDevice#2
N
Conversion
fromDevice#2
N
Conversion
fromDevice#2
N
High-Z
High-Z
Conversion
fromDevice#3
N
Conversion
fromDevice#3
N
Conversion
fromDevice#3
N
Don'tCare
Don'tCare
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ADS8331, ADS8332
www.ti.com
SBAS363D – DECEMBER 2009 – REVISED OCTOBER 2015
Case 1: If chip select is not toggled (CS stays low), the next 16 bits of data are from the upstream converter, and
so on. This configuration is shown in Figure 47.
Case 2: If the chip select is toggled during a daisy-chain mode data transfer cycle, as illustrated in Figure 48, the
same data from the converter are read out again and again in all three discrete 16-bit cycles. This state is not a
desired result.
Figure 48. Simplified Daisy-Chain Mode Timing With Shared CONVST and Noncontinuous CS
Copyright © 2009–2015, Texas Instruments Incorporated
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Product Folder Links: ADS8331 ADS8332



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