VS6955CA datasheet(61/90 Pages) STMICROELECTRONICS

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VS6955CA

Video timing

7.1.9

Framerate

The framerate of the array readout and therefore the output framerate is governed by the

line length, frame length and the video timing pixel clock frequency.

•

Line length is specified as a number of pixel clocks, line_length_pck.

•

Frame length is specified as a number of lines, frame_length_lines.

•

Video timing pixel clock is specified in MHz, vt_pix_clk_freq_mhz.

The equation relating the framerate to the Line length, frame length and the video timing

pixel clock frequency is given below:.

The maximum frame rate that can be achieved in profile 0 for RAW10 is 18 fps with CSI2

single lane. Table 34 provides an example of frame timing for RAW10 mode for 18 fps.

Table 35 provides an example of frame timing for 10-8 mode for 23 fps with CSI-2 single

lane.

7.1.10

Derating

To provide a wide range of data rate reduction options, the full image scaler is able to

reduce the data and therefore data rates in both the horizontal and vertical directions. In the

VS6955CA this is achieved by the use of a FIFO between video timing and output clock

domains.

It is therefore necessary for the host to configure the OP clock domain to ensure that the

FIFO neither over flows or under flows.

Framerate

vt_pix_clk_freq_mhz

line_length_pck

frame_length_lines

--------------------------------------------------------------------------------------------------

Table 34. External clock frequency example - 5.0 Mpixel RAW10 18 fps (CSI-2 single lane)

Ext clk

freq

Pre-PLL

clk div

PLL

multiplier

VT sys

clk div

VT pixel

clk div

VT pixel

clock

OP sys

clk div

OP pixel

clk div

OP pixel

clock

Line

length

Frame

length

MHz

Integer

(Dec)

Integer

MHz

Integer

MHz

Pixel

Clks

Lines

(Dec)

9.60

208

99.84

2750

1976

Table 35. External clock frequency examples - 5.0 Mpixel 10-8 23 fps (CSI-2 single lane)

Ext clk

freq

Pre-PLL

clk div

PLL

multiplier

VT sys

clk div

VT pixel

clk div

VT pixel

clock

OP sys

clk div

OP pixel

clk div

OP pixel

clock

Line

length

Frame

length

MHz

Integer

(Dec)

Integer

MHz

Integer

MHz

Pixel

Clks

Lines

(Dec)

9.60

208

124.8

2750

1976

VS6955CA Datasheet(PDF) 61 Page - STMicroelectronics

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