TMS320F28374DPTPS datasheet(32/212 Pages) TI1

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TMS320F28379D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880F – DECEMBER 2013 – REVISED NOVEMBER 2015

www.ti.com

Table 4-1. Signal Descriptions (continued)

TERMINAL

ZWT

PTP

PZP

I/O/Z(1)

DESCRIPTION

MUX

NAME

BALL

POSITION

NO.

GPIO158

0, 4, 8, 12

I/O

General-purpose input/output 158

C10

–

EPWM7B

Enhanced PWM7 output B (HRPWM-capable)

GPIO159

0, 4, 8, 12

I/O

General-purpose input/output 159

D10

–

EPWM8A

Enhanced PWM8 output A (HRPWM-capable)

GPIO160

0, 4, 8, 12

I/O

General-purpose input/output 160

–

EPWM8B

Enhanced PWM8 output B (HRPWM-capable)

GPIO161

0, 4, 8, 12

I/O

General-purpose input/output 161

–

EPWM9A

Enhanced PWM9 output A

GPIO162

0, 4, 8, 12

I/O

General-purpose input/output 162

–

EPWM9B

Enhanced PWM9 output B

GPIO163

0, 4, 8, 12

I/O

General-purpose input/output 163

–

EPWM10A

Enhanced PWM10 output A

GPIO164

0, 4, 8, 12

I/O

General-purpose input/output 164

–

EPWM10B

Enhanced PWM10 output B

GPIO165

0, 4, 8, 12

I/O

General-purpose input/output 165

–

EPWM11A

Enhanced PWM11 output A

GPIO166

0, 4, 8, 12

I/O

General-purpose input/output 166

–

EPWM11B

Enhanced PWM11 output B

GPIO167

0, 4, 8, 12

I/O

General-purpose input/output 167

–

EPWM12A

Enhanced PWM12 output A

GPIO168

0, 4, 8, 12

I/O

General-purpose input/output 168

–

EPWM12B

Enhanced PWM12 output B

RESET

Device Reset (in) and Watchdog Reset (out). The

devices have a built-in power-on reset (POR) circuit.

During a power-on condition, this pin is driven low by the

device. An external circuit may also drive this pin to

assert a device reset. This pin is also driven low by the

MCU when a watchdog reset or NMI watchdog reset

occurs. During watchdog reset, the XRS pin is driven low

XRS

F19

124

I/OD

for the watchdog reset duration of 512 OSCCLK cycles.

A resistor with a value from 2.2 k

Ω to 10 kΩ should be

placed between XRS and VDDIO. If a capacitor is placed

between XRS and VSS for noise filtering, it should be

100 nF or smaller. These values will allow the watchdog

to properly drive the XRS pin to VOL within 512 OSCCLK

cycles when the watchdog reset is asserted. The output

buffer of this pin is an open drain with an internal pullup.

CLOCKS

On-chip crystal-oscillator input. To use this oscillator, a

quartz crystal must be connected across X1 and X2. If

G19

123

this pin is not used, it must be tied to GND.

This pin can also be used to feed a single-ended 3.3-V

level clock. In this case, X2 is a No Connect (NC).

On-chip crystal-oscillator output. A quartz crystal may be

J19

121

connected across X1 and X2. If X2 is not used, it must

be left unconnected.

NO CONNECT

No connect. BGA ball is electrically open and not

–

connected to the die.

Terminal Configuration and Functions

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Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D

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