TMS320F28374DPTPS datasheet(97/212 Pages) TI1

97 / 212 page

TMS320F28379D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

www.ti.com

SPRS880F – DECEMBER 2013 – REVISED NOVEMBER 2015

Table 5-42. ADC Characteristics (16-Bit Differential Mode)

over recommended operating conditions (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ADC conversion cycles(2)

29.6

ADCCLKs

Power-up time (after setting

500

µs

ADCPWDNZ to first conversion)

Gain error

–64

±9

LSBs

Offset error(3)

–16

±9

LSBs

Channel-to-channel gain error

±6

LSBs

Channel-to-channel offset error

±3

LSBs

ADC-to-ADC gain error

Identical VREFHI and VREFLO for all ADCs

±6

LSBs

ADC-to-ADC offset error

Identical VREFHI and VREFLO for all ADCs

±3

LSBs

DNL(4)

> –1

±0.5

LSBs

INL

–3

±1.5

LSBs

SNR(5)(6)

VREFHI = 2.5 V, fin = 10 kHz

87.6

THD(5)(6)

VREFHI = 2.5 V, fin = 10 kHz

–93.5

SFDR(5)(6)

VREFHI = 2.5 V, fin = 10 kHz

95.4

SINAD(5)(6)

VREFHI = 2.5 V, fin = 10 kHz

86.6

VREFHI = 2.5 V, fin = 10 kHz,

14.1

single ADC(7)

VREFHI = 2.5 V, fin = 10 kHz,

ENOB(5)(6)

14.1

bits

synchronous ADCs(8)

VREFHI = 2.5 V, fin = 10 kHz,

not

asynchronous ADCs(9)

supported

VDDA = 3.3-V DC + 200 mV

PSRR

DC up to Sine at 1 kHz

VDDA = 3.3-V DC + 200 mV

PSRR

Sine at 800 kHz

CMRR

DC to 1 MHz

VREFHI input current

190

µA

VREFHI = 2.5 V, synchronous ADCs

(8)

–2

ADC-to-ADC isolation(6)(10)(11)

LSBs

not

VREFHI = 2.5 V, asynchronous ADCs

(9)

supported

(1)

Typical values are measured with VREFHI = 2.5 V and VREFLO = 0 V. Minimum and Maximum values are tested or characterized with

VREFHI = 2.5 V and VREFLO = 0 V.

(2)

See Section 5.8.1.1.2.

(3)

Difference from conversion result 32768 when ADCINp = ADCINn = VREFCM.

(4)

No missing codes.

(5)

AC parameters will be impacted by clock source accuracy and jitter, this should be taken into account when selecting the clock source

for the system. The clock source used for these parameters was a high-accuracy external clock fed through the PLL. The on-chip

Internal Oscillator has higher jitter than an external crystal and these parameters will degrade if it is used as a clock source.

(6)

IO activity is minimized on pins adjacent to ADC input and VREFHI pins as part of best practices to reduce capacitive coupling and

crosstalk.

(7)

One ADC operating while all other ADCs are idle.

(8)

All ADCs operating with identical ADCCLK, S+H durations, triggers, and resolution.

(9)

Any ADCs operating with heterogeneous ADCCLK, S+H durations, triggers, or resolution.

(10) Maximum DC code deviation due to operation of multiple ADCs simultaneously.

(11) Value based on characterization.

Specifications

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