TMS320F28374DPTPS datasheet(83/212 Pages) TI1

83 / 212 page

TMS320F28379D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

www.ti.com

SPRS880F – DECEMBER 2013 – REVISED NOVEMBER 2015

5.7.9.3

EMIF Electrical Data and Timing

5.7.9.3.1 Asynchronous RAM

Table 5-37 shows the EMIF asynchronous memory timing requirements. Table 5-38 shows the EMIF

asynchronous memory switching characteristics. Figure 5-20 through Figure 5-23 show the EMIF

asynchronous memory timing diagrams.

Table 5-37. EMIF Asynchronous Memory Timing Requirements

NO.

MIN

MAX

UNIT

Reads and Writes

EMIF clock period

tc(SYSCLK)

Pulse duration, EMxWAIT assertion and

tw(EM_WAIT)

deassertion

Reads

tsu(EMDV-EMOEH)

Setup time, EMxD[y:0] valid before EMxOE high

th(EMOEH-EMDIV)

Hold time, EMxD[y:0] valid after EMxOE high

Setup Time, EMxWAIT asserted before end of

tsu(EMOEL-EMWAIT)

Strobe Phase(1)

Writes

Setup Time, EMxWAIT asserted before end of

tsu(EMWEL-EMWAIT)

Strobe Phase(1)

(1)

Setup before end of STROBE phase (if no extended wait states are inserted) by which EMxWAIT must be asserted to add extended

wait states. Figure 5-21 and Figure 5-23 describe EMIF transactions that include extended wait states inserted during the STROBE

phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where

the HOLD phase would begin if there were no extended wait cycles.

Table 5-38. EMIF Asynchronous Memory Switching Characteristics(1)(2)(3)

NO.

PARAMETER

MIN

MAX

UNIT

Reads and Writes

td(TURNAROUND)

Turn around time

(TA)*E–3

(TA)*E+2

Reads

EMIF read cycle time (EW = 0)

(RS+RST+RH+2)*E–3

(RS+RST+RH+2)*E+2

tc(EMRCYCLE)

(RS+RST+RH+2+

EMIF read cycle time (EW = 1)

(EWC*16))*E–3

(EWC*16))*E+2

Output setup time, EMxCS[y:2] low

(RS)*E–3

(RS)*E+2

to EMxOE low (SS = 0)

tsu(EMCEL-EMOEL)

Output setup time, EMxCS[y:2] low

–3

to EMxOE low (SS = 1)

Output hold time, EMxOE high to

(RH)*E–3

(RH)*E

EMxCS[y:2] high (SS = 0)

th(EMOEH-EMCEH)

Output hold time, EMxOE high to

–3

EMxCS[y:2] high (SS = 1)

Output setup time, EMxBA[y:0]

tsu(EMBAV-EMOEL)

(RS)*E–3

(RS)*E+2

valid to EMxOE low

Output hold time, EMxOE high to

th(EMOEH-EMBAIV)

(RH)*E–3

(RH)*E

EMxBA[y:0] invalid

Output setup time, EMxA[y:0] valid

tsu(EMAV-EMOEL)

(RS)*E–3

(RS)*E+2

to EMxOE low

(1)

TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,

MEWC = Maximum external wait cycles. These parameters are programmed through the Asynchronous Bank and Asynchronous Wait

Cycle Configuration Registers. These support the following ranges of values: TA[4–1], RS[16–1], RST[64–4], RH[8–1], WS[16–1],

WST[64–1], WH[8–1], and MEWC[1–256]. See the TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual

(SPRUHM8) for more information.

(2)

E = EMxCLK period in ns.

(3)

EWC = external wait cycles determined by EMxWAIT input signal. EWC supports the following range of values. EWC[256–1]. Note that

the maximum wait time before time-out is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the

TMS320F2837xD Dual-Core Delfino Microcontrollers Technical Reference Manual (SPRUHM8) for more information.

Specifications

Submit Documentation Feedback

Product Folder Links: TMS320F28379D TMS320F28377D TMS320F28376D TMS320F28375D TMS320F28374D

TMS320F28374DPTPS Datasheet(PDF) 83 Page - Texas Instruments

TMS320F28374DPTPS Datasheet(HTML) 83 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL