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TMS320F28374DPTPS Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320F28374DPTPS Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 212 page  Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TMS320F28379D, TMS320F28377D TMS320F28376D, TMS320F28375D, TMS320F28374D SPRS880F – DECEMBER 2013 – REVISED NOVEMBER 2015 TMS320F2837xD Dual-Core Delfino™ Microcontrollers 1 Device Overview 1.1 Features 1 – Two Multichannel Buffered Serial Ports • Dual-Core Architecture (McBSPs) – Two TMS320C28x 32-Bit CPUs – Four Serial Communications Interfaces – 200 MHz (SCI/UART) (Pin-Bootable) – IEEE 754 Single-Precision Floating-Point Unit – Two I2C Interfaces (Pin-Bootable) (FPU) • Analog Subsystem – Trigonometric Math Unit (TMU) – Up to Four Analog-to-Digital Converters (ADCs) – Viterbi/Complex Math Unit (VCU-II) • 16-Bit Mode • Two Programmable Control Law Accelerators – 1.1 MSPS Each (up to 4.4-MSPS System (CLAs) Throughput) – 200 MHz – Differential Inputs – IEEE 754 Single-Precision Floating-Point – Up to 12 External Channels Instructions • 12-Bit Mode – Executes Code Independently of Main CPU – 3.5 MSPS Each (up to 14-MSPS System • On-Chip Memory Throughput) – 512KB (256KW) or 1MB (512KW) of Flash – Single-Ended Inputs (ECC-Protected) – Up to 24 External Channels – 172KB (86KW) or 204KB (102KW) of RAM (ECC-Protected or Parity-Protected) • Single Sample-and-Hold (S/H) on Each ADC – Dual-Zone Security Supporting Third-Party • Hardware-Integrated Post-Processing of Development ADC Conversions • Clock and System Control – Saturating Offset Calibration – Two Internal Zero-Pin 10-MHz Oscillators – Error From Setpoint Calculation – On-Chip Crystal Oscillator – High, Low, and Zero-Crossing Compare, With Interrupt Capability – Windowed Watchdog Timer Module – Trigger-to-Sample Delay Capture – Missing Clock Detection Circuitry – Eight Windowed Comparators With 12-Bit • 1.2-V Core, 3.3-V I/O Design Digital-to-Analog Converter (DAC) References • System Peripherals – Three 12-Bit Buffered DAC Outputs – Two External Memory Interfaces (EMIFs) With • Enhanced Control Peripherals ASRAM and SDRAM Support – 24 Pulse Width Modulator (PWM) Channels – Dual 6-Channel Direct Memory Access (DMA) With Enhanced Features Controllers – 16 High-Resolution Pulse Width Modulator – Up to 169 Individually Programmable, (HRPWM) Channels Multiplexed General-Purpose Input/Output (GPIO) Pins With Input Filtering • High Resolution on Both A and B Channels of 8 PWM Modules – Expanded Peripheral Interrupt Controller (ePIE) • Dead-Band Support (on Both Standard and – Multiple Low-Power Mode (LPM) Support With High Resolution) External Wakeup – Six Enhanced Capture (eCAP) Modules • Communications Peripherals – Three Enhanced Quadrature Encoder Pulse – USB 2.0 (MAC + PHY) (eQEP) Modules – Support for 12-Pin 3.3 V-Compatible Universal – Eight Sigma-Delta Filter Module (SDFM) Input Parallel Port (uPP) Interface Channels, 2 Parallel Filters per Channel – Two Controller Area Network (CAN) Modules (Pin-Bootable) • Standard SDFM Data Filtering – Three High-Speed (up to 50-MHz) SPI Ports • Comparator Filter for Fast Action for Out of (Pin-Bootable) Range 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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