TMS320F28374DPTPS datasheet(64/212 Pages) TI1

64 / 212 page

TMS320F28379D, TMS320F28377D

TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880F – DECEMBER 2013 – REVISED NOVEMBER 2015

www.ti.com

5.7.4

Flash Parameters

The on-chip flash memory is tightly integrated to the CPU, allowing code execution directly from flash

through 128-bit-wide prefetch reads and a pipeline buffer. Flash performance for sequential code is equal

to execution from RAM. Factoring in discontinuities, most applications will run with an efficiency of

approximately 80% relative to code executing from RAM. This flash efficiency lets designers realize a 2×

improvement in performance when migrating from the previous generation Delfino MCUs.

This device also has an OTP (One-Time-Programmable) sector used for the dual code security module

(DCSM), which cannot be erased after it is programmed.

Table 5-19 shows the minimum required flash wait states at different frequencies. Table 5-20 shows the

flash parameters at 200 MHz. Table 5-21 shows the flash/OTP endurance. Table 5-22 shows the flash

data retention duration.

Table 5-19. Minimum Required Flash Wait States at

Different Frequencies

FLASH WAIT STATES

CPUCLK (MHz)(1)

(MINIMUM REQUIRED RWAIT)

151–200

101–150

51–100

≤50

(1)

When using INTOSC (see Table 5-18, Internal Oscillator Electrical

Characteristics) as the PLL clock source, the SYSCLK divided by

RWAIT + 1 should not exceed 50 MHz after accounting for INTOSC

accuracy. For example, instead of configuring the PLL for 100 MHz,

configure it for 97 MHz when using INTOSC.

Table 5-20. Flash Parameters at 200 MHz(1)

PARAMETER

MIN

TYP

MAX

UNIT

128 data bits + 16 ECC bits

300

µs

Program Time(2)

8KW sector

180

32KW sector

360

720

8KW sector

Erase Time(3)

at < 25 cycles

32KW sector

8KW sector

105

4000

Erase Time(3)

at 50k cycles

32KW sector

110

4000

(1)

The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required

prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent

programming operations.

(2)

Program time includes overhead of the Flash state machine but does not include the time to transfer the following into RAM:

•

Code that uses Flash API to program the Flash

•

Flash API itself

•

Flash data to be programmed

In other words, the time indicated in this table is applicable after all the required code/data is available in the device RAM, ready for

programming. Note that the transfer time will significantly vary depending on the speed of the emulator used.

Program time calculation is based on programming 144 bits at a time at the specified operating frequency. Program time includes

Program verify by the CPU. Note that the program time does not degrade with write/erase (W/E) cycling, but the erase time does.

Erase time includes Erase verify by the CPU and does not involve any data transfer.

(3)

Erase time includes Erase verify by the CPU.

Specifications

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