 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMP320C2811PBKA Datasheet(PDF) 70 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TMP320C2811PBKA Datasheet(HTML) 70 Page - Texas Instruments |
|
|
70 / 147 page  Peripherals 70 June 2004 SPRS257 Table 4−7. McBSP Register Summary (Continued) NAME ADDRESS 0x00 78xxh TYPE (R/W) RESET VALUE (HEX) DESCRIPTION MULTICHANNEL CONTROL REGISTERS (CONTINUED) RCERE 17 R/W 0x0000 McBSP Receive Channel Enable Register Partition E RCERF 18 R/W 0x0000 McBSP Receive Channel Enable Register Partition F XCERE 19 R/W 0x0000 McBSP Transmit Channel Enable Register Partition E XCERF 1A R/W 0x0000 McBSP Transmit Channel Enable Register Partition F RCERG 1B R/W 0x0000 McBSP Receive Channel Enable Register Partition G RCERH 1C R/W 0x0000 McBSP Receive Channel Enable Register Partition H XCERG 1D R/W 0x0000 McBSP Transmit Channel Enable Register Partition G XCERH 1E R/W 0x0000 McBSP Transmit Channel Enable Register Partition H FIFO MODE REGISTERS (applicable only in FIFO mode) FIFO Data Registers‡ DRR2 00 R 0x0000 McBSP Data Receive Register 2 − Top of receive FIFO − Read First FIFO pointers will not advance DRR1 01 R 0x0000 McBSP Data Receive Register 1 − Top of receive FIFO − Read Second for FIFO pointers to advance DXR2 02 W 0x0000 McBSP Data Transmit Register 2 − Top of transmit FIFO − Write First FIFO pointers will not advance DXR1 03 W 0x0000 McBSP Data Transmit Register 1 − Top of transmit FIFO − Write Second for FIFO pointers to advance FIFO Control Registers MFFTX 20 R/W 0xA000 McBSP Transmit FIFO Register MFFRX 21 R/W 0x201F McBSP Receive FIFO Register MFFCT 22 R/W 0x0000 McBSP FIFO Control Register MFFINT 23 R/W 0x0000 McBSP FIFO Interrupt Register MFFST 24 R/W 0x0000 McBSP FIFO Status Register † DRR2/DRR1 and DXR2/DXR1 share the same addresses of receive and transmit FIFO registers in FIFO mode. ‡ FIFO pointers advancing is based on order of access to DRR2/DRR1 and DXR2/DXR1 registers. 4.6 Serial Communications Interface (SCI) Module R281x devices include two serial communications interface (SCI) modules. The SCI modules support digital communications between the CPU and other asynchronous peripherals that use the standard non-return-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the full-duplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baud-select register. Features of each SCI module include: • Two external pins: − SCITXD: SCI transmit-output pin − SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
