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TMP320C2811PBKA Datasheet(PDF) 90 Page - Texas Instruments |
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TMP320C2811PBKA Datasheet(HTML) 90 Page - Texas Instruments |
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90 / 147 page  Electrical Specifications 90 June 2004 SPRS257 6.12 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on R281x DSPs. Table 6−2 lists the cycle times of various clocks. Table 6−2. TMS320R281x Clock Table and Nomenclature MIN NOM MAX UNIT On chip oscillator clock tc(OSC), Cycle time 28.6 50 ns On-chip oscillator clock Frequency 20 35 MHz XCLKIN tc(CI), Cycle time 6.67 250 ns XCLKIN Frequency 4 150 MHz SYSCLKOUT tc(SCO), Cycle time 6.67 500 ns SYSCLKOUT Frequency 2 150 MHz XCLKOUT tc(XCO), Cycle time 6.67 2000 ns XCLKOUT Frequency 0.5 150 MHz HSPCLK tc(HCO), Cycle time 6.67 13.3‡ ns HSPCLK Frequency 75‡ 150 MHz LSPCLK tc(LCO), Cycle time 13.3 26.6‡ ns LSPCLK Frequency 37.5‡ 75 MHz ADC clock tc(ADCCLK), Cycle time† 40 ns ADC clock Frequency 25 MHz SPI clock tc(SPC), Cycle time 50 ns SPI clock Frequency 20 MHz McBSP tc(CKG), Cycle time 50 ns McBSP Frequency 20 MHz XTIMCLK tc(XTIM), Cycle time 6.67 ns XTIMCLK Frequency 150 MHz † The maximum value for ADCCLK frequency is 25 MHz. For SYSCLKOUT values of 25 MHz or lower, ADCCLK has to be SYSCLKOUT/2 or lower. ADCCLK = SYSCLKOUT is not a valid mode for any value of SYSCLKOUT. ‡ This is the default reset value if SYSCLKOUT = 150 MHz. 6.13 Clock Requirements and Characteristics 6.13.1 Input Clock Requirements The clock provided at the XCLKIN pin generates the internal CPU clock cycle. Table 6−3. Input Clock Frequency PARAMETER MIN TYP MAX UNIT Resonator 20 35 fx Input clock frequency Crystal 20 35 MHz fx Input clock frequency XCLKIN 4 150 MHz fl Limp mode clock frequency 2 MHz |
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