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DP83848JSQ/NOPB Datasheet(PDF) 6 Page - Texas Instruments |
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DP83848JSQ/NOPB Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 84 page  DP83848H, DP83848J, DP83848K, DP83848M, DP83848T SNLS250E – MAY 2008 – REVISED APRIL 2015 www.ti.com 4.2 Package Pin Assignments NSQAU040 PIN NAME NSQAU040 PIN NAME PIN # (DP83848J) PIN # (DP83848J) 1 IO_VDD 21(1) LED_SPEED/AN1 2 TX_CLK 22 LED_LINK/AN0 3 TX_EN 23 RESET_N 4 TXD_0 24 MDIO 5 TXD_1 25 MDC 6 TXD_2 26 IOVDD33 7 TXD_3 27 X2 8 RESERVED 28 X1 9 RESERVED 29 DGND 10 RESERVED 30 PFBIN2 11 RD– 31 RX_CLK 12 RD+ 32 RX_DV/MII_MODE 13 AGND 33 CRS/CRS_DV/LED_CFG 14 TD – 34 RX_ER/MDIX_EN 15 TD + 35 COL/PHYAD0 16 PFBIN1 36 RXD_0/PHYAD1 17 AGND 37 RXD_1/PHYAD2 18 AVDD33 38 RXD_2/PHYAD3 19 PFBOUT 39 RXD_3/PHYAD4 20 RBIAS 40 IOGND (1) Pin 21 is the CLK_OUT pin for the DP83848H/M/T. 4.3 Serial Management Interface SIGNAL TYPE PIN # DESCRIPTION NAME MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output MDC I 25 serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be MDIO I/O 24 sourced by the station management entity or the PHY. This pin requires a 1.5-k Ω pullup resistor. 4.4 Mac Data Interface SIGNAL TYPE PIN # DESCRIPTION NAME MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half-Duplex Modes. While in 10BASE-T Half-Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1 µs at the end of transmission to indicate heartbeat (SQE test). COL S, O, PU 35 In Full Duplex Mode, for 10 Mb/s or 100 Mb/s operation, this signal is always logic 0. There is no heartbeat function during 10Mb/s full duplex operation. RMII COLLISION DETECT: Per the RMII Specification, no COL signal is required. The MAC will recover CRS from the CRS_DV signal and use that along with its TX_EN signal to determine collision. MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. CRS/CRS_D RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and S, O, PU 33 V Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification. MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode. RX_CLK O 31 Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for both transmit and receive. 6 Pin Configuration and Functions Copyright © 2008–2015, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: DP83848H DP83848J DP83848K DP83848M DP83848T |
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