TMS320C6472ECTZ datasheet(158/269 Pages) TI1

158 / 269 page

TMS320C6472

SPRS612G

– JUNE 2009 – REVISED JULY 2011

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7.8.3.8

PLL1 PLLDIV Ratio Change Status Register (DCHANGE)

Whenever a different ratio is written to the PLLDIV10 register, the PLLCTRL flags the change in the

PLLDIV ratio change status register (DCHANGE). During the GO operation, the PLL controller will only

change the divide ratio of the SYSCLK with the bit set in DCHANGE. Note that changed clocks will be

automatically aligned to other clocks if the corresponding ALN bit is set. The PLLDIV divider ratio change

status register is shown in Figure 7-21 and described in Table 7-27.

Reserved

R-0

Reserved

SYSCLK10

Reserved

R-0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Figure 7-21. PLLDIV Divider Ratio Change Status Register (DCHANGE)

Table 7-27. PLLDIV Divider Ratio Change Status Register (DCHANGE) Field Descriptions

Bit

Field

Value

Description

31:10

Reserved

Reserved. The reserved bit location is always read as 0. A value written to these fields has no

effect.

SYSCLK10

Identifies when the SYSCLK10 divide ratio has been modified.

SYSCLK10 ratio has not been modified. When GOSET is set, SYSCLK10 will not be affected.

SYSCLK10 ratio has been modified. When GOSET is set, SYSCLK10 will change to the new ratio.

8:0

Reserved

Reserved. The reserved bit location is always read as 0. A value written to these fields has no

effect.

158

C64x+ Peripheral Information and Electrical Specifications

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