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TMS320C6472ECTZ Datasheet(PDF) 246 Page - Texas Instruments

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Part # TMS320C6472ECTZ
Description  TMS320C6472 Fixed-Point Digital Signal Processor
PDF  269 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320C6472ECTZ Datasheet(HTML) 246 Page - Texas Instruments

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background image
P48
H1
H2
H3
N
1Fh
N+1
N+2
N
N+1
N+2
12
11
9
10
14
8
7
6
5
URCLK
(input)
URDATA[15:0]
(input)
URADDR[4:0]
(input)
URCLA
(output)
V
URENB
(input)
URSOC
(input)
13
15
1Fh
1Fh
TMS320C6472
SPRS612G
– JUNE 2009 – REVISED JULY 2011
www.ti.com
Table 7-146. Timing Requirements for UTOPIA Slave Receive Cycles
(see Figure 7-63)
500/625/700
NO.
UNIT
MIN
MAX
5
tsu(URDATA−URCLKH)
Setup time, URDATA valid before URCLK high
4
ns
6
th(URCLKH−URDATA)
Hold time, URDATA valid after URCLK high
1
ns
7
tsu(URADDR−URCLKH)
Setup time, URADDR valid before URCLK high
4
ns
8
th(URCLKH−URADDR)
Hold time, URADDR valid after URCLK high
1
ns
9
tsu(URENB−URCLKH)
Setup time, URENB valid before URCLK high
4
ns
10
th(URCLKH−URENB)
Hold time, URENB valid after URCLK high
1
ns
11
tsu(URSOC−URCLKH)
Setup time, URSOC valid before URCLK high
4
ns
12
th(URCLKH−URSOC)
Hold time, URSOC valid after URCLK high
1
ns
Table 7-147. Switching Characteristics Over Recommended Operating Conditions for UTOPIA Slave
Receive Cycles
(see Figure 7-63)
500/625/700
NO.
PARAMETER
UNIT
MIN
MAX
13(1)
td(URCLKH−URCLAV)
Delay time, URCLK high to URCLAV valid
2
10
ns
14(1)
ten(URCLKH−URCLAV)
Enable time, URCLK high to URCLAV driven
2
10
ns
15(2) (3) tdis(URCLKL−URCLAVZ)
Disable time, URCLK low to URCLAV high-impedance state
2
10
ns
(1)
MAX delay time and enable time increases to 12.5 ns at 20 pF and 14 ns at 30 pF, specified by design.
(2)
Specifed by design for MIN values.
(3)
Specifed by design for MAX values.
Figure 7-63. UTOPIA Slave Receive
246
C64x+ Peripheral Information and Electrical Specifications
Copyright
© 2009–2011, Texas Instruments Incorporated
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Product Folder Link(s) :TMS320C6472



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