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TUSB3200A Datasheet(PDF) 49 Page - Texas Instruments |
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TUSB3200A Datasheet(HTML) 49 Page - Texas Instruments |
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49 / 102 page  TUSB3200A www.ti.com SLES018B – OCTOBER 2001 – REVISED FEBRUARY 2011 Figure 3-1. External Interrupt Timing Waveform 3.6 USB Transceiver Signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tr Transition rise time for DP or DM 4 20 ns tf Transition fall time for DP or DM 4 20 ns tRFM Rise/fall time matching (tr/tf) × 100 90% 110% 90% 110% VO(CRS) Voltage output signal crossover 1.3 2 V Figure 3-2. USB Differential Driver Timing Waveform 3.7 Codec Port Interface Signals (AC '97 Modes) TA = 25°C, DVDD = 3.3 V, DVDSS = 5 V, AVDD = 3.3 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fBIT_CLK Frequency, BIT_CLK (1) 12.288 MHz tcyc1 Cycle time, BIT_CLK (1) 81.4 ns tw1(H) Pulse duration, BIT_CLK high(1) 36 40.7 45 ns tw1(L) Pulse duration, BIT_CLK low (1) 36 40.7 45 ns fSYNC Frequency, SYNC CL = 50 pF 48 kHz tcyc2 Cycle time, SYNC CL = 50 pF 20.8 µs tw2 (H) Pulse duration, SYNC high CL = 50 pF 1.3 µs tw2(L) Pulse duration, SYNC low CL = 50 pF 19.5 µs Propagation delay time, BIT_CLK rising edge to CL = 50 pF tpd1 15 ns SYNC, SD_OUT, and RESET tsu Setup time, SD_IN to BIT_CLK falling edge CL = 50 pF 10 ns th Hold time, SD_IN from BIT_CLK falling edge 10 ns (1) Worst case duty cycle is 45/55. Figure 3-3. BIT_CLK Timing Waveform Copyright © 2001–2011, Texas Instruments Incorporated Electrical Specifications 49 Submit Documentation Feedback Product Folder Link(s): TUSB3200A |
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