TUSB3200A datasheet(14/102 Pages) TI1

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TUSB3200A

SLES018B – OCTOBER 2001 – REVISED FEBRUARY 2011

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1.6

Terminal Functions

− Normal Mode

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AVDD

3.3-V Analog supply voltage

AVSS

Analog ground

CSCLK

I/O

Codec port interface serial clock: CSCLK is the serial clock for the codec port interface used to clock

the CSYNC, CDATO, CDATI, CRESET, and CSCHNE signals. This signal uses a 5-V compatible

TTL/LVCMOS input/output buffer.

CSYNC

I/O

Codec port interface frame sync: CSYNC is the frame synchronization signal for the codec port

interface. This signal uses a 5-V compatible TTL/LVCMOS input/output buffer.

CDATO

I/O

Codec port interface serial data output: See Section 1.9 for details. This signal uses a 5-V compatible

TTL/LVCMOS input/output buffer.

CDATI

I/O

Codec port interface serial data input: See Section 1.9 for details. This signal uses a 5-V compatible

TTL/LVCMOS input/output buffer.

CRESET

I/O

Codec port interface reset output: See Section 1.9 for details. This signal uses a 5-V compatible

TTL/LVCMOS input/output buffer.

CSCHNE

I/O

Codec port interface secondary channel enable: See Section 1.9 for details. This signal uses a 5-V

compatible TTL/LVCMOS input/output buffer.

I/O

USB differential pair data signal plus: DP is the positive signal of the bidirectional USB differential pair

used to connect the TUSB3200A device to the universal serial bus.

I/O

USB differential pair data signal minus: DM is the negative signal of the bidirectional USB differential

pair used to connect the TUSB3200A device to the universal serial bus.

DVDD

9, 21,

3.3-V digital supply voltage

DVDDS

27, 43

5-V digital supply voltage

DVSS

5, 16,

Digital ground

33, 46

EXTEN

External MCU mode enable: Input used to enable the device for the external MCU mode. This signal

uses a 3.3-V TTL/LVCMOS input buffer.

MCLKI

Master clock input: An input that can be used as the master clock for the codec port interface or the

source for MCLKO2. This signal uses a 5-V to 3.3-V level-shifting input buffer.

MCLKI2

Master clock input 2: An input that can be used as the master clock for the codec port interface or the

source for MCLKO2. This signal uses a 5-V to 3.3-V level-shifting input buffer.

MCLKO

Master clock output: The output of the ACG that can be used as the master clock for the codec port

interface and the codec. This signal uses a 3.3-V TTL/LVCMOS output buffer.

MCLKO2

Master clock output 2: An output that can be used as the master clock for the codec port interface and

the codec. This clock signal can also be used as a miscellaneous clock. This signal uses a 3.3-V

TTL/LVCMOS output buffer.

MRESET

Master reset: An active low asynchronous reset for the device that resets all logic to the default state.

This signal uses a 3.3-V TTL/LVCMOS input buffer.

Not Used

This pin is not used in the normal mode. This signal should be tied to digital ground for normal

operation.

P1.0

I/O

General-purpose I/O port 1 bit 0: A bidirectional I/O port. This signal uses a 5-V compatible