DS2155 datasheet(84/262 Pages) DALLAS

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DS2156

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13.2 Path Code Violation Count Register (PCVCR)

13.2.1

T1 Operation

The path code violation count register records Ft, Fs, or CRC6 errors in T1 frames. When the receive side

of a framer is set to operate in the T1 ESF framing mode, PCVCR records errors in the CRC6 codewords.

When set to operate in the T1 D4 framing mode, PCVCR counts errors in the Ft framing bit position.

Through the ERCNT.2 bit, a framer can be programmed to also report errors in the Fs framing bit

position. The PCVCR is disabled during receive loss-of-synchronization (RLOS = 1) conditions. Table

13-C shows what errors the PCVCR counts.

Table 13-C. T1 Path Code Violation Counting Arrangements

FRAMING MODE

COUNT Fs ERRORS?

COUNTED

IN THE PCVCRs

Errors in the Ft pattern

Yes

Errors in both the Ft and Fs patterns

ESF

Don’t Care

Errors in the CRC6 codewords

13.2.2

E1 Operation

The path code violation-count register records CRC4 errors. Since the maximum CRC4 count in a one-

second period is 1000, this counter cannot saturate. The counter is disabled during loss-of-sync at either

the FAS or CRC4 level; it continues to count if loss-of-multiframe sync occurs at the CAS level.

Path code violation-count register 1 (PCVCR1) is the most significant word and PCVCR2 is the least

significant word of a 16-bit counter that records path violations (PVs).

PCVCR1

Path Code Violation Count Register 1

44h

Bit #

Name

PCVC15

PCVC14

PCVC13

PCVC12

PCVC11

PCVC10

PCVC9

PCVC8

Default

Bits 0 to 7/Path Code Violation Counter Bits 8 to 15 (PCVC8 to PCVC15). PCVC15 is the MSB of the 16-bit

path code violation count.

PCVCR2

Path Code Violation Count Register 2

45h

Bit #

Name

PCVC7

PCVC6

PCVC5

PCVC4

PCVC3

PCVC2

PCVC1

PCVC0

Default

Bits 0 to 7/Path Code Violation Counter Bits 0 to 7 (PCVC0 to PCVC7). PCVC0 is the LSB of the 16-bit path

code violation count.

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