PC87310 datasheet(20/52 Pages) NSC

20 / 52 page

40 Functional Description (Continued)

44 FLOPPY DISK CONTROLLER

441 Introduction

This device contains a full featured floppy disk controller

that is software compatible with the mPD765A and the

DP8473 It includes many hardware and software enhance-

ments Among these enhancements is additional logic spe-

cifically required for an IBM PC PC-XT or PS2 design

This controller incorporates a precision analog data separa-

tor that includes a self trimming delay line and VCO Up to

three external filters are switched automatically depending

on the data rate selected This provides optimal perform-

ance at the standard PC data rates fo 250300 kbs and

500 kbs It also enables optimum performance at 1 Mbs

(MFM) These features combine to provide the lowest possi-

ble PLL bandwidth with the greatest lock range and hence

the widest window margin

This controller has write precompensation circuitry A shift

pensation for all tracks at 500k300k250 kbs (83 ns for

1 MBs) or a precompensation value that scales with the

data rate 83 ns125 ns208 ns250 ns for data rates of

10M500k300k250 kbs respectively

Specifically to support the PC-AT and PC-XT design the

Floppy Disk Controller PLUS-2 includes address decode for

the A0 – A2 address lines the motordrive select register

data rate register for selecting 250300500 kbs Disk

Changed status dual speed spindle motor control low write

current and DMAinterrupt sharing logic The controller also

supports direct connection to the mP bus via internal 24 mA

buffers The controller also can be connected directly to the

disk drive via internal open drain high drive outputs and

Schmitt inputs

In addition to this logic the controller includes many features

to ease design of higher performance drives and future con-

troller upgrades These include 10 Mbs data rate extend-

ed track range to 4096 Implied seeking working Scan Com-

mands motor control timing both standard IBM formats as

well as Sony 35

(ISO) formats and other enhancements

442 765A Compatible Micro-Engine

The core of the FDC is a mPD765A and DP8473 compatible

microcoded engine This engine consists of a sequencer

program ROM and diskmisc registers This core is clocked

by either a 4 MHz 48 MHz or 8 MHz clock selected in the

Data Rate Register Upon this core is added all the glue

logic used to implement a PC-XT or AT or PS2 floppy con-

troller as well as the data separator and write precompen-

sation logic

The controller consists of a microcoded engine that controls

the entire operation of the chip including coordination of

data transfer with the CPU controlling the drive controls

and actually performing the algorithms associated with

reading and writing data tofrom the disk This includes the

read algorithm for the data separator

Like the mPD765A this controller takes commands and re-

turns data and status through the Data Register in a byte

serial fashion Handshake for commandstatus IO is pro-

vided via the Main Status Register All of the mPD765A

commands are supported as are many other enhanced

commands

DATA SEPARATOR

The internal data separator consists of an analog PLL and

its associated circuitry The PLL synchronizes the raw data

signal read from the disk drive The synchronized signal is

used to separate the encoded clock and data pulses The

data pulses are de-serialized into bytes and then sent to the

P by the controller

The main PLL consists of four main components a phase

comparator a filter a voltage controlled oscillator (VCO)

and a programmable divider The phase comparator detects

the difference between the phase of the divider’s output and

the phase of the raw data being read from the disk This

phase difference is converted to a current which either

charges or discharges one of the three external filters The

resulting voltage on the filter changes the frequency of the

VCO and the divider output to reduce the phase difference

between the input data and the divider’s output The PLL is

‘‘locked’’ when the frequency of the divider is exactly the

same as the average frequency of the data read from the

disk A block diagram of the data separator is shown in

Fig-

ure 2

PC87310 Datasheet(PDF) 20 Page - National Semiconductor (TI)

PC87310 Datasheet(HTML) 20 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

Datasheet Download

Link URL