PC87310 datasheet(27/52 Pages) NSC

27 / 52 page

40 Functional Description (Continued)

445 Processor Software Interface

Bytes are transferred to and from the disk controller in dif-

ferent ways for the different phases in a command

COMMAND SEQUENCE

The disk controller can perform various disk transfer and

head movement commands Most commands involve three

separate phases

Command Phase

The mP writes a series of bytes to the

Data Register These bytes indicate the command desired

and the particular parameters required for the command All

the bytes must be written in the order specified in the Com-

mand Description Table The Execution Phase starts imme-

diately after the last byte in the Command Phase is written

Prior to performing the Command Phase the Drive Control

and Data Rate Registers should be set

Execution Phase

The disk controller performs the desired

command Some commands require the mP to read or write

data to or from the Data Register during this time Reading

data from a disk is an example of this

Result Phase

The mP reads a series of bytes from the data

cuted properly and other pertinent information The bytes

are read in the order specified in the Command Description

Table

A new command may be initiated by writing the Command

Phase bytes after the last bytes required from the Result

Phase have been read If the next command requires se-

lecting a different drive or changing the data rate the Drive

Control and Data Rate Registers should be updated If the

command is the last command then the software should

deselect the drive

(Note as a general rule the operation of

the controller core is independent of how the mP updates

the Drive Control and Data Rate Registers The software

must ensure that manipulation of these registers is coordi-

nated with the controller operation)

During the Command Phase and the Result Phase bytes

are transferred to and from the Data Register The Main

Status Register is monitored by the software to determine

when a data transfer can take place Bit 6 of the Main

Status Register must be clear and bit 7 must be set before a

byte can be written to the Data Register during the Com-

mand Phase Bits 6 and 7 of the Main Status Register must

both be set before a byte can be read from the Data Regis-

ter during the Result Phase

If there is information to be transferred during the Execution

Phase there are three methods that can be used The DMA

mode is used if the system has a DMA controller This al-

lows the mP to do other things during the Execution Phase

data transfer If DMA is not used an interrupt can be issued

for each byte transferred during the Execution Phase If in-

terrupts are not used the Main Status Register can be

polled to indicate when a byte transfer is required

DMA MODE

If the DMA mode is selected a DMA request will be gener-

ated in the Execution Phase when each byte is ready to be

transferred To enable DMA operations during the Execu-

tion Phase the DMA mode bit in the Specify Command

must be enabled and the DMA signals must be enabled in

the Drive Control Register The DMA controller should re-

spond to the DMA request with a DMA acknowledge and a

read or write strobe The DMA request will be cleared by the

active edge of the DMA acknowledge After the last byte is

transferred an interrupt is generated indicating the begin-

ning of the Result Phase During DMA operations the Chip

Select input must be held high TC is asserted to terminate

an operation Due to the internal gating TC is only recog-

nized when the DAK input is low

INTERRUPT MODE

If the non-DMA mode is selected an interrupt will be gener-

ated in the Execution Phase when each byte is ready to be

transferred The Main Status Register should be read to ver-

ify that the interrupt is for a data transfer Bits 5 and 7 of the

Main Status Register will be set The interrupt will be

cleared when the byte is transferred to or from the Data

allotted by Table 4-14 If the byte is not transferred within

the time allotted an Overrun Error will be indicated in the

Result Phase when the command terminates at the end of

the current sector

An interrupt will also be generated after the last byte is

transferred This indicates the beginning of the Result

Phase Bits 7 and 6 of the Main Status Register will be set

and bit 5 will be clear This interrupt will be cleared by read-

ing the first byte in the Result Phase

Interrupt Type

Reg Bits e

mP Clearing Action

Result Phase Start

MSR7 6 5 e 1 1 0

Read 1 status byte from

the Data Register (Result)

Data Write

MSR7 6 5 e 1 0 1

Write 1 data byte to the

Data Register (Execution)

Data Read

MSR7 6 5 e 1 1 1

Read 1 data byte from the

Data Register (Execution)

Reset (Note)

MSR7 6 5 e 1 0 0

Issue a Sense Interrupt

command after reset

Seek (Note)

MSR7 6 5 e 1 0 0

Issue a Sense Interrupt command

after a Seek

Recalibrate (Note)

MSR7 6 5 e 1 0 0

Issue a Sense Interrupt command

after a Recalibrate

Note

These 3 interrupts are identified by reading Status Register 0 after issuing a sense-interrupt command

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