PC87310 datasheet(24/52 Pages) NSC

24 / 52 page

40 Functional Description (Continued)

either 4 MHz 48 MHz and 8 MHz to be input as the master

clock for the controller core If the Drive Type pin is high and

a 300 kbs data rate is chosen 48 MHz is used to generate

300 kbs but when the DRVTYP pin is low and 300 kbs is

selected 4 MHz is used and the actual data rate is

250 kbs See Table 4-12

Low Power Mode Logic

This logic is an enhancement

over the standard XT AT PS2 design In the Low Power

Mode the crystal oscillator the FDC both UARTs and all

linear circuitry are turned off The internal FDC circuitry is

disabled while the oscillator is off because the internal cir-

cuitry is driven from this clock The oscillator will turn back

on automatically after it detects a read or a write to the Main

Status or Data Registers It may take a few milli-seconds for

the oscillator to stabilize and the mP will be prevented from

trying to access the Data Register during this time through

the normal Main Status Register protocol (The Request for

Master bit in the Main Status Register will be inactive) Dur-

ing the oscillator stabilization period the software should poll

the Main Status Register until the Request for Master bit is

set The low power mode is programmed through the Mode

Command

The Data Rate Register and the Drive Control Register are

unaffected by the power down mode They will remain ac-

tive It is up to the user to ensure that the Motor and Drive

select signal are turned off The ESDI interface will be inac-

tive All of the registers will remain unchanged

The UART registers are unaffected by the power down

mode however their serial data sections will be inoperative

The parallel port address decoder and configuration regis-

ter are unaffected by the power down mode

Note

In addition to the manual low power mode an automatic low power

mode is incorporated on this part This automatic low power mode is

unsupported by NSC and we recommend that it not be used because

it may result in lost data during UART operation

TABLE 4-11 Truth Table for Drive Control Register

(Configuration Register Bit 7 e 0)

Function

Drive 0 Selected (DR0 e 0)

X1X0

Drive 1 Selected (DR1 e 0)

Not Available

Crystal Oscillator

The FDC is clocked by a single 24 MHz

signal An on-chip oscillator is provided to enable the at-

tachment of a crystal or a clock If a crystal is used a

24 MHz fundamental mode parallel resonant crystal should

be used This crystal should be specified to have less than

50X series resistance and shunt capacitance of less than

7 pF

If an external oscillator circuit is used it must have a duty

cycle of 40 – 60% and minimum input levels of 24V and

04V The controller should be configured so that the clock

is input into the OSC2 pin and OSC1 is tied to ground

Crystal

SaRonix SRX 3164

TABLE 4-12 Summary of FDC Registers

Bits

DCR (W)

MTR3

MTR2

MTR1

MTR0

DMA

Software

Drive

Enable

Reset

Select 1

Select 0

MSR (R)

Request

Expected

Non-DMA

Command

Drive 3

Drive 2

Drive 1

Drive 0

for

Data

Execution

Seeking

Master

Direction

Progress

DR (RW)

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

DRR (W)

Data Rate

Bit 1

Bit 0

DKR (R)

DSKCHG

Inverse

ST0

Data

Seek

Head

DRV 1

DRV 0

IRQ6 Code

End

Track 0

Addr

(Exec)

ST1

EOT Bit

CRC

Data

WRT

Missing

No TC

Error

Overrun

Data

PRT

Address

Mark

ST2

Control

CRC

WRG

Scan

Bad

Missing

Mark

Error in

Track

Equal

Not

Track

Address

Data Fld

Hit

Satisfied

Mark in

Data Fld

ST3

Write

Track 0

Head

DRV 1

DRV 0

Protect

Status

Select

(Exec)

Status

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