PC87310 datasheet(19/52 Pages) NSC

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40 Functional Description (Continued)

TABLE 4-7 Interrupt Control Functions

Interrupt Identification

Priority

Level

Interrupt Set and Reset Functions

Bit 2

Bit 1

Bit 0

Interrupt Type

Interrupt Source

Interrupt Reset Control

None

Highest

Receiver Line Status

Overrun Error or Parity

Reading the Line

Error or Framing Error

Status Register

or Break Interrupt

Second

Received Data Available

Receiver Data Available

Reading the Receiver

Buffer Register

Third

Transmitter Holding

Reading the IIR Register

(if source of interrupt) or

Writing into the Trans-

mitter Holding Register

Fourth

MODEM Status

Clear to Send or Data

Reading the MODEM

Set Ready or Ring

Status Register

Indicator or Data

Carrier Detect

Bit 1

This bit controls the Request to Send (RTS) output

Bit 1 affects the RTS output in a manner identical to that

described above for bit 0 In local loopback mode this bit

controls bit 4 of the MODEM Status Register

Bit 2

This bit is the OUT1 bit It does not have an output pin

associated with it It can be written to and read by the CPU

In local loopback mode this bit controls bit 6 of the Modem

Status Register

Bit 3

This bit enables the interrupt when set No external

pin is associated with this bit In local loopback mode this

bit controls bit 7 of the MODEM Status Register

Bit 4

This bit provides a local loopback feature for diagnos-

tic testing of the UART When bit 4 is set to logic 1 the

following occur the transmitter Serial Output (SOUT) is set

to the Marking (logic 1) state the receiver Serial Input (SIN)

is disconnected the output of the Transmitter Shift Register

is ‘‘looped back’’ into the Receiver Shift Register input the

four MODEM Control inputs (DSR CTS RI and DCD) are

disconnected and the DTR RTS OUT1 IRQ ENABLE bits

in MCR are internally connected to DSR CTS RI and DCD

in MSR respectively When operating in the AT mode the

MODEM Control output pins are forced to their high (inac-

tive) states When operating in the XT mode the Modem

Control output pins remain connected to their correspond-

ing bits in the MCR In the loopback mode data that is

transmitted is immediately received This feature allows the

processor to verify the transmit-and-received-data paths of

the serial port

In the loopback mode the receiver and transmitter inter-

rupts are fully operational The MODEM Status Interrupts

are also operational but the interrupts’ sources are the low-

er four bits of MCR instead of the four MODEM control in-

puts Writinga1toany of them will cause an interrupt The

interrupts are still controlled by the Interrupt Enable Regis-

ter

Bits 5 through 7

These bits are permanently set to logic 0

MODEM STATUS REGISTER

This register provides the current state of the control lines

from the MODEM (or peripheral device) to the CPU In addi-

tion to this current-state information four bits of the MO-

DEM Status Register provide change information These

bits are set to a logic 1 whenever a control input from the

MODEM changes state They are reset to logic 0 whenever

the CPU reads the MODEM Status Register

Table 4-4 shows the contents of the MSR Details on each

bit follow

Bit 0

This bit is the Delta Clear to Send (DCTS) indicator

Bit 0 indicates that the CTS input to the chip has changed

state since the last time it was read by the CPU

Bit 1

This bit is the Delta Data Set Ready (DDSR) indicator

Bit 1 indicates that the DSR input to the chip has changed

state since the last time it was read by the CPU

Bit 2

This bit is the Trailing Edge of Ring Indicator (TERI)

detector Bit 2 indicates that the RI input to the chip has

changed from a low to a high state

Bit 3

This bit is the Delta Data Carrier Detect (DDCD) indi-

cator Bit 3 indicates that the DCD input to the chip has

changed state

Note

Whenever bit 0 1 2 or 3 is set to logic 1 a MODEM Status Interrupt

is generated

Bit 4

This bit is the complement of the Clear to Send (CTS)

input If bit 4 (loopback) of the MCR is set to a 1 this bit is

equivalent to RTS in the MCR

Bit 5

This bit is the complement of the Data Set Ready

(DSR) input If bit 4 of the MCR is set to a 1 this bit is

equivalent to DTR in the MCR

Bit 6

This bit is the complement of the Ring Indicator (RI)

input If bit 4 of the MCR is set to a 1 this bit is equivalent to

OUT 1 in the MCR

Bit 7

This bit is the complement of the Data Carrier Detect

(DCD) input If bit 4 of the MCR is set to a 1 this bit is

equivalent to IRQ ENABLE in the MCR

SCRATCHPAD REGISTER

This 8-bit ReadWrite Register does not control the UART

in any way It is intended as a scratchpad register to be used

by the programmer to hold data temporarily When operat-

ing in the XT mode this register is unavailable

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