PC87310 datasheet(23/52 Pages) NSC

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40 Functional Description (Continued)

Filter capacitor in series with R2 With pump current

this determines loop bandwidth

Filter resistor Determines the PLL damping factor

This filter capacitor improves the performance of the

PLL by providing additional filtering of bit jitter and

noise

KVCO The ratio of the change in the frequency of the VCO

output due to a voltage change at the VCO input

KVCO

25 MradsV The VCO is followed by a di-

vider to achieve the desired frequency for each data

rate VCO center frequency is 4 MHz for data rates

of 1 Mbs 500 kbs and 250 kbs (MFM) and is

48 MHz for 300 kbs (MFM)

KPLL This is the gain of the internal PLL circuitry and is

the product of VREF c KVCO c KP This value is

specified in the Phase Locked Loop Characteristics

table

This is the bandwidth of the PLL and is given by

0n e

0 KPLL

2qC2NR1

where N is the number of VCO cycles between two

phase comparisons The value of N for the various

data rates are shown in Table 4-9

The damping factor is set to 07 to 12 and is given

g e

0nR2C2

The trade off when choosing filter components is between

acquisition time while the PLL is locking and jitter immunity

while reading data To select the proper components for a

standard floppy disk application the following procedure can

be used

1 Choose FM or MFM and data rate Determine N from

Table 4-9 Determine preamble length (MFM e 12) The

PLL should lock within

the preamble time

2 Determine loop bandwidth (0n) required and set the

charge pump resistor R1

3 Calculate C2 using

C2 e

KPLL

2qR1N0n2

4 Choose R2 using

R2 e

0nC2

6 Select C1 to be about

th of C2

The above procedure will yield adequate loop performance

If optimum loop performance is required or if the nature of

the loop performance is very critical then some additional

consideration must be given to choosing 0n and the damp-

ing factor (For a detailed description on how to choose 0n

and g see AN-505 Floppy Disk Data Separator Design

Guide for the DP8473)

WRITE PRECOMPENSATION

The FDC incorporates a single fixed 3-bit shift register This

shift register outputs are tapped and multiplexed onto the

write data output The taps are selected by a standard pre-

compensation algorithm This precompensation value can

be selected from the PUMPPREN pin When this pin is low

125 ns precomp is used for all data rates except 1 Mbs

which uses 83 ns When PREN is tied high the precompen-

sation-value scales with data rate at 250 kbs its 250 ns for

300 kbs its 208 ns at 500 kbs its 125 ns and at 10 Mbs

its 83 ns These values are shown in Table 4-13

PC-AT AND PC-XT LOGIC BLOCKS

This section describes the major functional blocks of the PC

logic that have been integrated on the controller Refer back

to the block diagram 12

DMA Enable Logic

This is gating logic that disables the

DMA lines and the Interrupt output under the control of the

DMA Enable bit in the Drive control register When the DMA

Enable bit is 0 then the INT and DRQ are held TRI-STATE

and DAK is disabled

Drive Output BuffersInput Receivers

The drive inter-

face output pins can drive 150X g10% termination resis-

tors This enables connection to a standard floppy drive All

drive interface inputs are TTL compatible schmitt trigger in-

puts with typically 250 mV of hysteresis

The MTR2 and 3

and DR2 and 3 pins have been removed in order to accom-

modate the 100 pin package

Bus Interface-Address Decode

The address decode cir-

cuit allows software access to the controller Drive Control

memory map) using the same address map as is used in the

XT AT or PS2 The decoding is provided for A0 – A2 so

only a single address decoder connected to the chip select

is needed to complete the decode The bus interface logic

includes the 8-bit data bus and DRQINT signals The out-

put drive for these pins is 24 mA

TABLE 4-10 Address Memory Map for DP8473

Addr

03F0

None (Bus TRI-STATE)

03F1

None (Bus TRI-STATE)

03F2

Drive Control (DCR)

03F3

None (Bus TRI-STATE)

03F4

Main Status (MSR)

03F5

Data (DR)

03F6

None (Bus TRI-STATE)

03F7

Data Rate (DRR)

03F7

Disk Changed Bit (DKR)

When this location is accessed only bit D7 is driving all others are held in

TRI-STATE

Drive Control Register

This 8-bit write only register con-

trols the drive selects motor enables DMA enable and Re-

set See Register Description

Reset Logic

The reset input pin is active high and directly

feeds the Drive Control Register and the Data Rate Regis-

ter After a hardware reset the Drive Control Register is re-

set to all zeros and the Data Rate Register is set to

250 kbs data rate The controller is held reset until the

software sets the Drive Control reset bit after which the

controller may be initialized A software reset to the control-

ler core can be issued by resetting then setting this bit A

software reset does not reset the Drive Control Register or

the Data Rate Register

Data Rate Register and Clock Logic

This is a two bit

See Register Description This register feeds logic that se-

lects the data rates by programming a prescaler that divides

the crystal or clock input by either 3 5 or 6 This causes

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