PC87310 datasheet(25/52 Pages) NSC

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40 Functional Description (Continued)

443 Register Description

This section describes the register bits for all the registers

that are directly accessible to the mP Table 4-10 shows the

memory map for these registers Note that in the PC some

of the registers are partially decoded this is not the case

here All registers occupy only their documented addresses

MAIN STATUS REGISTER (Read Only)

The read only Main Status Register indicates the current

status of the disk controller The Main Status Register is

always available to be read One of its functions is to control

the flow of data to and from the Data Register The Main

Status Register indicates when the disk contoller is ready to

send or receive data It should be read before each byte is

transferred to or from the Data Register except during a

DMA transfer No delay is required when reading this regis-

ter after a data transfer

D7 Request for Master

Indicates that the Data Register is

ready to send or receive data from the mP This bit is

cleared immediately after a byte transfer and will become

set again as soon as the disk controller is ready for the next

byte

D6 Data Direction

Indicates whether the controller is ex-

pecting a byte to be written to (0) or read from (1) the Data

D5 Non-DMA Execution

Bit is set only during the Execu-

tion Phase of a command if it is in the non-DMA mode In

other words if this bit is set the multiple byte data transfer

(in the Execution Phase) must be monitored by the mP ei-

ther through interrupts or software polling as described in

the Processor Software Interface section

D4 Command in Progress

Bit is set after the first byte of

the Command Phase is written Bit is cleared after the last

byte of the Result Phase is read If there is no result phase

in a command the bit is cleared after the last byte of the

Command Phase is written

D3 Drive 3 Seeking

Set after the last byte of the Command

Phase of a Seek or Recalibrate command is issued for drive

3 Cleared after reading the first byte in the Result Phase of

the Sense Interrupt Command for this drive

D2 Drive 2 Seeking

Same as above for drive 2

D1 Drive 1 Seeking

Same as above for drive 1

D0 Drive 0 Seeking

Same as above for drive 0

DATA REGISTER (ReadWrite)

This is the location through which all commands data and

status flow between the CPU and the FDC During the Com-

mand Phase the mP loads the controller’s commands into

this register based on the Status Register Request for Mas-

ter and Data Direction bits The Result Phase transfers the

Status Registers and header information to the mPinthe

same fashion

DRIVE CONTROL REGISTER (Write Only)

D7 Motor Enable 3

This controls the Motor for drive 3

MTR3 When 0 the output is inactive when 1 the output is

active (Note this signal is not output to a pin) This bit and

DCR bit 6 provide information that controls the MTR1 and 0

pins respectively when bit 7 of the Configuration Register is

set See Tables 4-2 and 4-11

D6 Motor Enable 2

Same function as D7 except for drive

2’s motor (Note this signal is not brought out to a pin)

D5 Motor Enable 1

This bit controls the Motor for drive 1’s

motor When this bit is 0 the MTR1 output is high

D4 Motor Enable 0

Same as D5 except for drive 0’s motor

D3 DMA Enable

When set to a 1 this enables the DRQ

DAK INT pins A zero disables these signals

D2 Reset Controller

This bit when set to a 0 resets the

controller and when a 1 enables normal operation It does

not affect the Drive Control or Data Rate Registers which

are reset only by a hardware reset

D1 – D0 Drive Select

These two pins are encoded for the

four drive selects and are gated with the motor enable

lines so that only one drive is selected when it’s Motor En-

able is active (See Table 4-11)

DATA RATE REGISTER (Write Only)

D7 – D2

Not used

D1 D0 Data Rate Select

These bits set the data rate and

the write precompensation values for the disk controller Af-

ter a hardware reset these bits are set to 10 (250 kbs)

They are encoded as shown in Table 4-13

DISK CHANGED REGISTER (Read Only)

D7 Disk Changed

This bit is the latched complement of the

Disk Changed input pin If the DSKCHG input is low this bit

is high

TABLE 4-13 Data Rate and Precompensation Programming Values

DRVTYP

Data Rate

Normal

Alternate

FGND

RPMLC

MFM

Precomp

(kbs)

(ns)

Enabled

Level

500

125

FGND500

High

250

125

250

FGND250

Low

300

208

FGND250

Low

250

125

250

FGND250

Low

250

125

250

FGND250

Low

1000

None

High

1000

None

Low

Normal values when PUMPPREN pin set low Alternate values when PUMPPREN pin set high

D0 and D1 are Data Rate Control Bits

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