PC87310 datasheet(15/52 Pages) NSC

15 / 52 page

40 Functional Description (Continued)

432 Serial Port Registers

Two identical register sets one for each channel are in the

DUART All register descriptions in this section apply to the

LINE CONTROL REGISTER

The system programmer uses the Line Control Register

(LCR) to specify the format of the asynchronous data com-

munications exchange and set the Divisor Latch Access bit

This is a read and write register Table 4-4 shows the con-

tents of the LCR Details on each bit follow

TLC10591 – 7

FIGURE 1 Composite Serial Data

Bits 0 and 1

These two bits specify the number of data bits

in each transmitted or received serial character The encod-

ing of bits 0 and 1 is as follows

Bit 1

Bit 0

Data Length

5 Bits

6 Bits

7 Bits

8 Bits

Bit 2

This bit specifies the number of Stop bits transmitted

with each serial character If bit 2 is a logic 0 one Stop bit is

generated in the transmitted data If bit 2 is a logic 1 when a

5-bit data length is selected one and a half Stop bits are

generated If bit 2 is a logic 1 when either a 6- 7- or 8-bit

word length is selected two Stop bits are generated The

receiver checks the first Stop bit only regardless of the

number of Stop bits selected

Bit 3

This bit is the Parity Enable bit When bit 3 is a logic 1

a Parity bit is generated (transmit data) or checked (receive

data) between the last data bit and Stop bit of the serial

data (The Parity bit is used to produce an even or odd

number of 1s when the data bits and the Parity bit are

summed)

Bit 4

This bit is the Even Parity Select bit When parity is

enabled and bit 4 is a logic 0 an odd number of logic 1s is

transmitted or checked in the data word bits and Parity bit

When parity is enabled and bit 4 is a logic 1 an even num-

ber of logic 1s is transmitted or checked

Bit 5

This bit is the Stick Parity bit When parity is enabled it

is used in conjunction with bit 4 to select Mark or Space

Parity When bits 3 4 and 5 are logic 1 the Parity bit is

transmitted and checked as a logic 0 (Space Parity) If bits 3

and 5 are 1 and bit 4 is a logic 0 then the Parity bit is

transmitted and checked as a logic 1 (Mark Parity) If bit 5 is

a logic 0 Stick Parity is disabled

Bit 6

This bit is the Break Control bit It causes a break

condition to be transmitted to the receiving UART When it

is set to a logic 1 the serial output (SOUT) is forced to the

Spacing state (logic 0) The break is disabled by setting bit 6

to a logic 0 The Break Control bit acts only on SOUT and

has no effect on the transmitter logic

Note

This feature enables the CPU to alert a terminal in a computer com-

munications system If the following sequence is followed no errone-

ous or extraneous characters will be transmitted because of the

break

1 Load an all 0s pad character in response to THRE

2 Set break after the next THRE

3 Wait for the transmitter to be idle (TEMT e 1) and clear break when

normal transmission has to be restored

During the break the Transmitter can be used as a character timer to accu-

rately establish the break duration

Bit 7

This bit is the Divisor Latch Access Bit (DLAB) It must

be set high (logic 1) to access the Divisor Latches of the

Baud Generator or the Alternate Function Register during a

Read or Write operation It must be set low (logic 0) to ac-

cess any other register

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