LAN8742AI-CZ datasheet(31/124 Pages) MICROCHIP

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DS00001989A-page 31

LAN8742A/LAN8742Ai

The MODE[2:0] hardware configuration pins are multiplexed with other signals as shown in Table 3-5.

3.7.3

REGOFF: INTERNAL +1.2 V REGULATOR CONFIGURATION

The incorporation of flexPWR technology provides the ability to disable the internal +1.2 V regulator. When the regulator

is disabled, an external +1.2 V must be supplied to the VDDCR pin. Disabling the internal +1.2 V regulator makes it

possible to reduce total system power, since an external switching regulator with greater efficiency (versus the internal

linear regulator) can be used to provide +1.2 V to the transceiver circuitry.

3.7.3.1

Disabling the Internal +1.2 V Regulator

To disable the +1.2 V internal regulator, a pull-up strapping resistor should be connected from the REGOFF configura-

tion strap to VDD2A. At power-on, after both VDDIO and VDD2A are within specification, the transceiver will sample

REGOFF to determine whether the internal regulator should turn on. If the pin is sampled at a voltage greater than VIH,

then the internal regulator is disabled and the system must supply +1.2 V to the VDDCR pin. The VDDIO voltage must

be at least 80% of the operating voltage level (1.44 V when operating at 1.8 V, 2.0 V when operating at 2.5 V, 2.64 V

when operating at 3.3 V) before voltage is applied to VDDCR. As described in Section 3.7.3.2, when REGOFF is left

floating or connected to VSS, the internal regulator is enabled and the system is not required to supply +1.2 V to the

VDDCR pin.

3.7.3.2

Enabling the Internal +1.2 V Regulator

The +1.2 V for VDDCR is supplied by the on-chip regulator unless the transceiver is configured for the regulator off mode

using the REGOFF configuration strap as described in Section 3.7.3.1. By default, the internal +1.2 V regulator is

enabled when REGOFF is floating (due to the internal pull-down resistor). During power-on, if REGOFF is sampled

below VIL, then the internal +1.2 V regulator will turn on and operate with power from the VDD2A pin.

110

Power-Down mode. In this mode the transceiver will

wake-up in Power-Down mode. The transceiver can-

not be used when the MODE[2:0] bits are set to this

mode. To exit this mode, the MODE bits in Register

18.7:5 (see Section 4.2.14, "Special Modes Register")

must be configured to some other value and a soft

reset must be issued.

N/A

111

All capable. Auto-negotiation enabled.

X10X

1111

TABLE 3-5:

PIN NAMES FOR MODE BITS

MODE Bit

Pin Name

MODE[0]

RXD0/MODE0

MODE[1]

RXD1/MODE1

MODE[2]

CRS_DV/MODE2

Note:

Because the REGOFF configuration strap shares functionality with the LED1 pin, proper consideration

must also be given to the LED polarity. Refer to Section 3.8.1, "LEDs" for additional information on the rela-

tion between REGOFF and the LED1 polarity.

TABLE 3-4:

MODE[2:0] BUS (CONTINUED)

MODE[2:0]

Mode Definitions

Default Register Bit Values

[13,12,10,8]

[8,7,6,5]

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