LAN8742AI-CZ datasheet(40/124 Pages) MICROCHIP

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LAN8742A/LAN8742Ai

DS00001989A-page 40

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3.8.3.2

Energy Detect Power-Down (EDPD)

This power-down mode is activated by setting the EDPWRDOWN bit of the Mode Control/Status Register. In this mode,

when no energy is present on the line the transceiver is powered down (except for the management interface, the

SQUELCH circuit, and the ENERGYON logic). The ENERGYON logic is used to detect the presence of valid energy

from 100BASE-TX, 10BASE-T, or Auto-negotiation signals.

In this mode, when the ENERGYON bit of the Mode Control/Status Register is low, the transceiver is powered-down

and nothing is transmitted. When energy is received via link pulses or packets, the ENERGYON bit goes high and the

transceiver powers-up. The device automatically resets into the state prior to power-down and asserts the nINT interrupt

if the ENERGYON interrupt is enabled in the Interrupt Mask Register. The first and possibly the second packet to acti-

vate ENERGYON may be lost.

When the EDPWRDOWN bit of the Mode Control/Status Register is low, energy detect power-down is disabled.

When in EDPD mode, the device’s NLP characteristics may be modified. The device can be configured to transmit NLPs

in EDPD via the EDPD TX NLP Enable bit of the EDPD NLP/Crossover TimeRegister. When enabled, the TX NLP time

interval is configurable via the EDPD TX NLP Interval Timer Select field of the EDPD NLP/Crossover TimeRegister.

When in EDPD mode, the device can also be configured to wake on the reception of one or two NLPs. Setting the EDPD

RX Single NLP Wake Enable bit of the EDPD NLP/Crossover TimeRegister will enable the device to wake on reception

of a single NLP. If the EDPD RX Single NLP Wake Enable bit is cleared, the maximum interval for detecting reception

of two NLPs to wake from EDPD is configurable via the EDPD RX NLP Max Interval Detect Select field of the EDPD

NLP/Crossover TimeRegister.

3.8.4

WAKE ON LAN (WOL)

The device supports PHY layer WoL event detection of Perfect DA, Broadcast, Magic Packet, and Wakeup frames. The

WoL detection can be configured to assert the nINT interrupt pin or nPME pin, providing a mechanism for a system in

sleep mode to return to an operational state when a WoL event occurs. This feature is particularly useful in addressing

unnecessary waking of the main SoC in designs where the Ethernet MAC is integrated into the SoC.

Each type of supported wake event (Perfect DA, Broadcast, Magic Packet, or Wakeup frames) may be individually

enabled via Perfect DA Wakeup Enable (PFDA_EN), Broadcast Wakeup Enable (BCST_EN), Magic Packet Enable

(MPEN), and Wakeup Frame Enable (WUEN) bits of the Wakeup Control and Status Register (WUCSR), respectively.

Two methods are provided for indicating a WoL event to an external device: nINT and nPME.

The nINT pin may be used to indicate WoL interrupt events by setting bit 8 (WoL) of the Interrupt Mask Register. Once

enabled, any received packet that matches the condition(s) configured in the Wakeup Control and Status Register

(WUCSR) will assert nINT until the interrupt is cleared. When using nINT to indicate a WoL interrupt, the pin may be

shared with other non-WoL interrupt events, as configured via the Interrupt Mask Register. While waiting for a WoL

event to occur, it is possible that other interrupts may be triggered. To prevent such conditions, all other interrupts shall

be masked by system software, or the alternative nPME pin may be used. Refer to Section 3.6, "Interrupt Management"

for additional nINT information.

Alternatively, the nPME pin may be used to independently indicate WoL interrupt events. The nPME signal can be con-

figured to output on any of the following pins:

• LED1/nINT/nPME/nREGOFF

• LED2/nINT/nPME/nINTSEL

The LED1/nINT/nPME/nREGOFF or LED2/nINT/nPME/nINTSEL pin can be configured to function as nPME by config-

uring the LED1 Function Select or LED2 Function Select bits of the Wakeup Control and Status Register (WUCSR) to

10b, respectively.Once the nPME pin is enabled, any received packet that matches the condition(s) configured in the

Wakeup Control and Status Register (WUCSR) will assert nPME until WUCSR bits 7:4 are cleared by the system soft-

ware. However, in some applications it may be desirable for nPME to self clear. When the nPME Self Clear bit of the

Wakeup Control and Status Register (WUCSR) is set, the nPME pin will clear after the time configured in the Miscella-

neous Configuration Register (MCFGR).

Upon a WoL event, further resolution on the source of the event can be obtained by examining the Perfect DA Frame

Received (PFDA_FR), Broadcast Frame Received (BCAST_FR), Magic Packet Received (MPR), and Remote Wakeup

Frame Received (WUFR) status bits in the Wakeup Control and Status Register (WUCSR).

Note:

In REF_CLK Out Mode, REFCLKO will not output when the device is in Energy Detect Power-Down Mode.

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