LAN8742AI-CZ datasheet(44/124 Pages) MICROCHIP

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LAN8742A/LAN8742Ai

DS00001989A-page 44

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CRC[6] = F1 ^ F3

CRC[5] = F2 ^ F4

CRC[4] = F3 ^ F5

CRC[3] = F4 ^ F6

CRC[2] = F5 ^ F7

CRC[1] = F6

CRC[0] = F7

Determine the offset pattern with offset 0 being the first byte of the destination address. Update the offset in the

Filter Pattern Offset field of the Wakeup Filter Configuration Register A (WUF_CFGA).

Determine Address Matching Conditions:

Determine the address matching scheme based on Table 3-7 and update the Filter Broadcast Enable, Filter Any

Multicast Enable, and Address Match Enable bits of the Wakeup Filter Configuration Register A (WUF_CFGA)

accordingly.

If necessary (see step 4), set the desired MAC address to cause the wake event in the MAC Receive Address A

(RX_ADDRC).

Set the Filter Enable bit of the Wakeup Filter Configuration Register A (WUF_CFGA) to enable the filter.

Enable Wakeup Frame Detection:

Set the Wakeup Frame Enable (WUEN) bit of the Wakeup Control and Status Register (WUCSR) to enable

Wakeup Frame detection.

Set bit 8 (WoL event indicator) in the Interrupt Mask Register to enable WoL events to trigger assertion of the

nINT interrupt pin.

When a match is triggered, the nINT interrupt pin will be asserted and the Remote Wakeup Frame Received (WUFR)

bit of the Wakeup Control and Status Register (WUCSR) will be set. To provide additional visibility to software, the Filter

Triggered bit of the Wakeup Filter Configuration Register A (WUF_CFGA) will be set.

3.8.5

ISOLATE MODE

The device data paths may be electrically isolated from the RMII interface by setting the Isolate bit of the Basic Control

respond to management transactions.

Isolation provides a means for multiple transceivers to be connected to the same RMII interface without contention. By

default, the transceiver is not isolated (on power-up (Isolate =0).

3.8.6

RESETS

The device provides two forms of reset: hardware and software. The device registers are reset by both hardware and

software resets. Select register bits, indicated as “NASR” in the register definitions, are not cleared by a software reset.

The registers are not reset by the power-down modes described in Section 3.8.3.

3.8.6.1

Hardware Reset

A hardware reset is asserted by driving the nRST input pin low. When driven, nRST should be held low for the minimum

time detailed in Section 5.6.3, "Power-On nRST & Configuration Strap Timing" to ensure a proper transceiver reset.

During a hardware reset, an external clock must be supplied to the XTAL1/CLKIN signal.

Note:

Alternatively, the LED1/nINT/nPME or LED2/nINT/nPME pin can be used to indicate a WoL event. Refer

to Section 3.8.4, "Wake on LAN (WoL)" for additional information.

Note:

For the first 16 µs after coming out of reset, the RMII interface will run at 2.5 MHz. After this time, it will

switch to 25 MHz if auto-negotiation is enabled.

Note:

A hardware reset (nRST assertion) is required following power-up. Refer to Section 5.6.3, "Power-On

nRST & Configuration Strap Timing" for additional information.

LAN8742Ai-CZ Datasheet(PDF) 44 Page - Microchip Technology

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