LAN8742AI-CZ datasheet(45/124 Pages) MICROCHIP

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DS00001989A-page 45

LAN8742A/LAN8742Ai

3.8.6.2

Software Reset

A Software reset is activated by setting the Soft Reset bit of the Basic Control Register to “1”. All registers bits, except

those indicated as “NASR” in the register definitions, are cleared by a Software reset. The Soft Reset bit is self-clearing.

Per the IEEE 802.3u standard, clause 22 (22.2.4.1.1) the reset process will be completed within 0.5 s from the setting

of this bit.

3.8.7

CARRIER SENSE

The carrier sense (CRS) is output on the CRS_DV pin. CRS is a signal defined by the MII specification in the IEEE

802.3u standard. The device asserts CRS based only on receive activity whenever the transceiver is either in repeater

mode or full-duplex mode. Otherwise the transceiver asserts CRS based on either transmit or receive activity.

The carrier sense logic uses the encoded, unscrambled data to determine carrier activity status. It activates carrier

sense with the detection of 2 non-contiguous zeros within any 10 bit span. Carrier sense terminates if a span of 10 con-

secutive ones is detected before a /J/K/ Start-of Stream Delimiter pair. If an SSD pair is detected, carrier sense is

asserted until either /T/R/ End–of-Stream Delimiter pair or a pair of IDLE symbols is detected. Carrier is negated after

the /T/ symbol or the first IDLE. If /T/ is not followed by /R/, then carrier is maintained. Carrier is treated similarly for IDLE

followed by some non-IDLE symbol.

3.8.8

LINK INTEGRITY TEST

The device performs the link integrity test as outlined in the IEEE 802.3u (clause 24-15) Link Monitor state diagram. The

link status is multiplexed with the 10 Mbps link status to form the Link Status bit in the Basic Status Register and to drive

the LINK LED (LED1).

The DSP indicates a valid MLT-3 waveform present on the RXP and RXN signals as defined by the ANSI X3.263 TP-

PMD standard, to the Link Monitor state-machine, using the internal DATA_VALID signal. When DATA_VALID is

asserted, the control logic moves into a Link-Ready state and waits for an enable from the auto-negotiation block. When

received, the Link-Up state is entered, and the Transmit and Receive logic blocks become active. Should auto-negoti-

ation be disabled, the link integrity logic moves immediately to the Link-Up state when the DATA_VALID is asserted.

To allow the line to stabilize, the link integrity logic will wait a minimum of 330 ms from the time DATA_VALID is asserted

until the Link-Ready state is entered. Should the DATA_VALID input be negated at any time, this logic will immediately

negate the Link signal and enter the Link-Down state.

When the 10/100 digital block is in 10BASE-T mode, the link status is derived from the 10BASE-T receiver logic.

3.8.9

CABLE DIAGNOSTICS

The LAN8742A/LAN8742Ai provides cable diagnostics which allow for open/short and length detection of the Ethernet

cable. The cable diagnostics consist of two primary modes of operation:

• Time Domain Reflectometry (TDR) Cable Diagnostics

TDR cable diagnostics enable the detection of open or shorted cabling on the TX or RX pair, as well as cable

length estimation to the open/short fault.

• Matched Cable Diagnostics

Matched cable diagnostics enable cable length estimation on 100 Mbps-linked cables.

Refer to the following sub-sections for details on proper operation of each cable diagnostics mode.

3.8.9.1

Time Domain Reflectometry (TDR) Cable Diagnostics

The LAN8742A/LAN8742Ai provides TDR cable diagnostics which enable the detection of open or shorted cabling on

the TX or RX pair, as well as cable length estimation to the open/short fault. To utilize the TDR cable diagnostics, Auto-

MDIX and Auto Negotiation must be disabled, and the LAN8742A/LAN8742Ai device must be forced to 100 Mb full-

duplex mode. These actions must be performed before setting the TDR Enable bit in the TDR Control/Status Register.

With Auto-MDIX disabled, the TDR will test the TX or RX pair selected by register bit 27.15 (AMDIXCTRL). Proper cable

testing should include a test of each pair. When TDR testing is complete, prior register settings may be restored. Figure

3-16 provides a flow diagram of proper TDR usage.

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