LAN8742AI-CZ datasheet(20/124 Pages) MICROCHIP

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LAN8742A/LAN8742Ai

DS00001989A-page 20

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3.1.2.7

Receive Data Valid Signal

The Receive Data Valid signal (RXDV) indicates that recovered and decoded nibbles are being presented on the

RXD[1:0] outputs synchronous to RXCLK. RXDV becomes active after the /J/K/ delimiter has been recognized and RXD

is aligned to nibble boundaries. It remains active until either the /T/R/ delimiter is recognized or link test indicates failure

or SIGDET becomes false.

RXDV is asserted when the first nibble of translated /J/K/ is ready for transfer over the Media Independent Interface (MII

mode).

3.1.2.8

Receiver Errors

During a frame, unexpected code-groups are considered receive errors. Expected code groups are the DATA set (0

through F), and the /T/R/ (ESD) symbol pair. When a receive error occurs, the RXER signal is asserted and arbitrary

data is driven onto the RXD[1:0] lines. Should an error be detected during the time that the /J/K/ delimiter is being

decoded (bad SSD error), RXER is asserted true and the value ‘1110’ is driven onto the RXD[1:0] lines. Note that the

Valid Data signal is not yet asserted when the bad SSD error occurs.

3.1.2.9

100M Receive Data Across the RMII Interface

The 2-bit data nibbles are sent to the RMII block. These data nibbles are clocked to the controller at a rate of 50 MHz.

The controller samples the data on the rising edge of XTAL1/CLKIN (REF_CLK).

3.1.3

10BASE-T TRANSMIT

Data to be transmitted comes from the MAC layer controller. The 10BASE-T transmitter receives 4-bit nibbles from the

MII at a rate of 2.5 MHz and converts them to a 10 Mbps serial data stream. The data stream is then Manchester-

encoded and sent to the analog transmitter, which drives a signal onto the twisted pair via the external magnetics.

The 10M transmitter uses the following blocks:

• MII (digital)

• TX 10M (digital)

• 10M Transmitter (analog)

• 10M PLL (analog)

3.1.3.1

10M Transmit Data Across the MII/RMII Interface

The MAC controller drives the transmit data onto the TXD bus. TXD[1:0] shall transition synchronously with respect to

REF_CLK. When TXEN is asserted, TXD[1:0] are accepted for transmission by the device. TXD[1:0] shall be “00” to

indicate idle when TXEN is deasserted. Values of TXD[1:0] other than “00” when TXEN is deasserted are reserved for

out-of-band signaling (to be defined). Values other than “00” on TXD[1:0] while TXEN is deasserted shall be ignored by

the device.TXD[1:0] shall provide valid data for each REF_CLK period while TXEN is asserted.

In order to comply with legacy 10BASE-T MAC/Controllers, in half-duplex mode the transceiver loops back the trans-

mitted data, on the receive path. This does not confuse the MAC/Controller since the COL signal is not asserted during

this time. The transceiver also supports the SQE (Heartbeat) signal.

FIGURE 3-3:

RELATIONSHIP BETWEEN RECEIVED DATA AND SPECIFIC MII SIGNALS

data data data data

RXD

RX_DV

RX_CLK

data data data data

CLEAR-TEXT

Idle

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