LPC18S50 datasheet(73/151 Pages) NXP

73 / 151 page

LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

73 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

• Programmable display resolution including, but not limited to: 320  200, 320  240,

640

 200, 640  240, 640  480, 800  600, and 1024  768.

• Hardware cursor support for single-panel displays.

• 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support.

• 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN.

• 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT.

• 16 bpp true-color non-palettized for color STN and TFT.

• 24 bpp true-color non-palettized for color TFT.

• Programmable timing for different display panels.

• 256 entry, 16-bit palette RAM, arranged as a 128  32-bit RAM.

• Frame, line, and pixel clock signals.

• AC bias signal for STN, data enable signal for TFT panels.

• Supports little and big-endian, and Windows CE data formats.

• LCD panel clock can be generated from the peripheral clock, or from a clock input pin.

7.13.10 Ethernet

Remark: Ethernet is available on parts LPC1850/30 (see Table 2).

7.13.10.1

Features

• 10/100 Mbit/s

• DMA support

• Power management remote wake-up frame and magic packet detection

• Supports both full-duplex and half-duplex operation

– Supports CSMA/CD Protocol for half-duplex operation.

– Supports IEEE 802.3x flow control for full-duplex operation.

– Optional forwarding of received pause control frames to the user application in

full-duplex operation.

– Back-pressure support for half-duplex operation.

– Automatic transmission of zero-quanta pause frame on deassertion of flow control

input in full-duplex operation.

• Support for IEEE 1588 time stamping and IEEE 1588 advanced time stamping (IEEE

1588-2008 v2).

7.14 Digital serial peripherals

7.14.1 UART

The LPC18S50/S30/S10 contain one UART with standard transmit and receive data lines.

UART1 also provides a full modem control handshake interface and support for

RS-485/9-bit mode allowing both software address detection and automatic address

detection using 9-bit mode.

UART1 includes a fractional baud rate generator. Standard baud rates such as 115200 Bd

can be achieved with any crystal frequency above 2 MHz.

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