LPC18S50 datasheet(87/151 Pages) NXP

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LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

87 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

IDD(IO)

I/O supply current

deep sleep mode

A

power-down mode

A

deep power-down mode

[8] -0.05

A

IDDA

Analog supply current

on pin VDDA;

deep sleep mode

[11] -0.4

A

power-down mode

[11] -0.4

A

deep power-down

mode

[11] -0.007

A

RESET,RTC_ALARM, WAKEUPn pins

VIH

HIGH-level input

voltage

[10] 0.8

 (V

ps 

0.35)

-5.5

VIL

LOW-level input voltage

[10] 0

0.3

 (V

ps 

0.1)

Vhys

hysteresis voltage

[10] 0.05

 (V

 0.35)

--V

output voltage

[10] -Vps - 0.2

Standard I/O pins - normal drive strength

input capacitance

ILL

LOW-level leakage

current

VI = 0 V; on-chip pull-up

resistor disabled

-3

-nA

ILH

HIGH-level leakage

current

VI =VDD(IO); on-chip

pull-down resistor

disabled

-3

-nA

VI = 5 V

--20

IOZ

OFF-state output

current

VO =0V to VDD(IO);

on-chip pull-up/down

resistors disabled;

absolute value

-3

-nA

input voltage

pin configured to provide

a digital function;

VDD(IO)  2.2 V

5.5

VDD(IO) = 0 V

3.6

output voltage

output active

VDD(IO)

VIH

HIGH-level input

voltage

0.7



VDD(IO)

-5.5

VIL

LOW-level input voltage

0.3



VDD(IO)

Vhys

hysteresis voltage

0.1



VDD(IO)

--V

VOH

HIGH-level output

voltage

IOH = 6 mA

VDD(IO) 

0.4

--V

VOL

LOW-level output

voltage

IOL = 6 mA

--0.4

IOH

HIGH-level output

current

VOH =VDD(IO)  0.4 V

6

--mA

Table 10.

Static characteristics …continued

Tamb = 40 C to +85 C unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

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