LPC18S50 datasheet(91/151 Pages) NXP

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LPC18S50_S30_S10

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Product data sheet

Rev. 1 — 23 February 2015

91 of 151

NXP Semiconductors

LPC18S50/S30/S10

32-bit ARM Cortex-M3 microcontroller

[1]

Typical ratings are not guaranteed. The values listed are at room temperature (25

C), nominal supply voltages.

[2]

Dynamic characteristics for peripherals are provided for VDD(REG)(3V3)  2.7 V.

[3]

Pin VPP should either be not connected (when OTP does not need to be programmed) or tied to pins VDDIO and VDDREG to ensure

the same ramp-up time for both supply voltages.

[4]

VDD(REG)(3V3) = 3.3 V; VDD(IO) = 3.3 V; Tamb =25 C.

Oscillator pins

Vi(XTAL1)

input voltage on pin

XTAL1

0.5

1.2

Vo(XTAL2)

output voltage on pin

XTAL2

0.5

1.2

Cio

input/output

capacitance

[17] --0.8

USB0 pins[18]

input voltage

on pins USB0_DP;

USB0_DM; USB0_VBUS

VDD(IO)  2.2 V

5.25

VDD(IO) = 0 V

3.6

Rpd

pull-down resistance

on pin USB0_VBUS



VIC

common-mode input

voltage

high-speed mode

50

200

500

full-speed/low-speed

mode

800

2500

chirp mode

50

600

Vi(dif)

differential input voltage

100

400

1100

USB1 pins (USB1_DP/USB1_DM)[18]

IOZ

OFF-state output

current

0V<VI <3.3 V

[18] --

10

A

VBUS

bus supply voltage

[19] --5.25

VDI

differential input

sensitivity voltage

(D+)  (D)

0.2

--V

VCM

differential common

mode voltage range

includes VDI range

0.8

2.5

Vth(rs)se

single-ended receiver

switching threshold

voltage

0.8

2.0

VOL

LOW-level output

voltage for

low-/full-speed

RL of 1.5 k to 3.6 V

0.18

VOH

HIGH-level output

voltage (driven) for

low-/full-speed

RL of 15 k to GND

2.8

3.5

Ctrans

transceiver capacitance pin to GND

ZDRV

driver output

impedance for driver

which is not high-speed

capable

with 33

 series resistor;

steady state drive

[20] 36

44.1



Table 10.

Static characteristics …continued

Tamb = 40 C to +85 C unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ[1]

Max

Unit

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