PPC34C60 datasheet(15/58 Pages) SMSC

15 / 58 page

SMSC DS – PPC34C60

Page 15

Rev. 06/01/2001

ADVANCED INFORMATION

3.2 Design Example

FIGURE 3 shows a simple system design that uses most of the PPC34C60's interface functions. This example shows:

A DRAM interface.

An 8Kx8 NV-memory device interface using nStrobe Output 0 to latch the upper address bits and nChip Select Output

0 to enable the device.

An interface to SMSC's FDC37C662 Super I/O Floppy Disk Controller. This section of the design illustrates how the

PPC34C60 can handle a direct memory access interface, four interrupts, and an additional chip select output

configured as a standard output pin. The SRST (reset output) is used to reset the floppy disk controller.

The use of 10K bias resistors to implement a product ID code.

FIGURE 3 - TYPICAL SYSTEM INTERFACE

PPC34C60

A[8:9]

A[0:7]

nWR

nOE

nRAS

nCAS

SD[0:7]

A[8:9]

A[0:7]

nWR

nOE

nRAS

nCAS

SD[8:15]

1Mx8 DRAM

374

D[0:7]

Q[0:7]

CLOCK

nOE

A[0:7]

A[8:12]

nWR

nOE

SD[0:7]

Optional, 8Kx8 SRAM

EEPROM, etc.

FDC37C662

D[0:7]

A[0:7]

A[8:9]

nIOW

nIOR

FDRQ

nDACK

IRQ3

IRQ4

PINTR

FINTR

AEN

RST

SD[0:15]

MA[8:9]

SA[0:7]

nSWR

nSRD

nRAS

nCAS

nIO16

nST0

nCE

nCS0

DREQ

nDACK

IN0

IN1

IN2

IN3

CS1

SRST

IRQ

UPPER

ADDRESS

LATCH

TEST

Xin

Xout

Yin

Yout

24MHz

KHz

nPID

Product

ID =

7BDEh

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