PPC34C60 datasheet(22/58 Pages) SMSC

22 / 58 page

SMSC DS – PPC34C60

Page 22

Rev. 06/01/2001

ADVANCED INFORMATION

SOUND REGISTER - 0011 (Write Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

FREQ

LTONE

STONE

SQULCH

rsvrd

These bits allow the piezo driver to generate tones under program control.

Bits 0-3:rsvrd

These bits are reserved and should be written as zeros.

Bit 4:SQULCH

Setting this bit terminates currently active low battery tones. If the low battery input (Pin 35) goes high, and then low again

after this bit is set, low battery tones will resume. In order to squelch these low battery tones, this bit simply needs to be

re-written with a logic "1".

Bit 5:STONE

Setting this bit generates a 1/8 second tone. This bit self-clears after the tone is generated and when set again will

generate another 1/8 second tone.

Bit 6:LTONE

Setting this bit generates a 1/2 second tone. This bit self-clears after the tone is generated and when set again will

generate another 1/2 second tone.

Bit 7:FREQ

This bit selects the Nominal frequency for the piezo driver circuit. 0 selects 2KHz, 1 selects 4 KHz .

INPUT REGISTER - 0011 (Read Only)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

LOBATT

IRQ

LATCH

QIC-80

IN3

IN2

IN1

IN0

The PPC34C60 has six Input pins, of which two are dedicated and four are uncommitted. The Input Register provides the

Host with bit access to each of these input pins. Bit 4 is a special purpose bit useful for QIC-80 tape drive peripherals.

Bit 0:IN0 (Pin 82)

This bit represents the current state of the uncommitted input pin IN0.

Bit 1:IN1 (Pin 83)

This bit represents the current state of the uncommitted input pin IN1.

Bit 2:IN2 (Pin 37)

This bit represents the current state of the uncommitted input pin IN2.

Bit 3:IN3 (Pin 36)

This bit represents the current state of the uncommitted input pin IN3.

Bit 4:QIC-80

This bit will be set if more than 2.5ms have passed since the last rising edge of IRQ (pin 48). This function is designed for

QIC-80 tape drives that require 2.5ms between the completion of one command and the start of a subsequent command.

Bit 5:IRQ LATCH

This bit is used to latch an interrupt request event and is enabled by setting INTEN (bit 6 of the Operation Register). When

enabled this bit is set by a rising edge on the IRQ pin (Pin 48), and cleared by setting INTCLR (bit 7of the Operation

Specification - Reference 3).

Bit 6:IRQ (Pin 48)

This bit represents the current state of the IRQ pin.

Bit 7:LOBATT (Pin 35)

This bit represents the current state of the LOBATT input. When low, the piezo driver circuitry will provide a "low battery

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