PPC34C60 datasheet(31/58 Pages) SMSC

31 / 58 page

SMSC DS – PPC34C60

Page 31

Rev. 06/01/2001

ADVANCED INFORMATION

SYSTEM DATA BUS CYCLES

The System Data Bus is controlled by an internal state machine with seven states as shown below in FIGURE 7. The state

machine is clocked by the BUSCLK which is software- programmable as SCLK divided by 2, 3, 5, or 6.

Three types of operations are performed by the bus interface: a Bus Cycle, a DRAM Access, and a DRAM Refresh. Refer

to Tables 4-6 for the state flow description for each operation. The bus controller normally sits in the idle state. When a bus

interface operation is kicked off, it advances to state 1. It then advances to the next state at every BUSCLK cycle. After

state 7, the controller returns to idle.

FIGURE 7 - GENERIC SYSTEM DATA BUS CYCLE

BUS CYCLE TIMING

When an Address Write cycle selects a bus write, the next data received is written to the bus. The interface must, however,

know whether to expect an 8 or 16 bit bus address. To determine the bus width, a bus cycle is started from the Address

Write cycle. This "pre-write" cycle asserts chip select and samples and latches nIO16. The write cycle is initiated after the

first byte received for 8 bit writes, or after the second byte of data for 16 bit writes.

Table 4 - Bus Cycle State Flow Description

IDLE

Write: Data bus drivers are disabled, nRAS and nCAS are inactive.

STATE 1

Read:

If necessary, data advances to next element in the FIFO buffer.

nCAS goes active for first refresh.

STATE 2

Write:

Data is latched into bus latches.

nRAS goes active for first refresh.

STATE 3

Chip Select goes active.

STATE 4

nIO16 is sampled.

Read:

nRD goes active.

Write:

If nIO16 is sampled low and this is the first byte received, then nWR remains inactive.

If nIO16 is sampled high or if nIO16 is sampled low and this is the second byte received,

then nWR goes active and data bus drivers are enabled.

nRAS and nCAS go inactive.

STATE 5

Wait for data bus to stabilize, nCAS goes active for second refresh.

STATE 6

Read:

Data is latched, nRD goes inactive.

Write:

nWR goes inactive.

nRAS goes active for second refresh.

STATE 7

Chip select goes inactive.

Read:

Data advances to next element if possible.

Write:

Data bus drivers are disabled.

Table 5 - DRAM Access State Flow Description

IDLE

nRAS and nCAS go inactive.

STATE 1

Row Address output.

STATE 2

nRAS goes active.

Read:

nRD goes active.

Write:

nWR goes active.

STATE 3

Column Address output

Write:

Data bus drivers enabled.

STATE 4

nCAS goes active.

STATE 5

Column Address incremented.

Read:

Data is latched.

Write:

Data bus drivers disabled.

(If multiple accesses are needed, States 3-5 are repeated)

STATE 6

nRAS, nCAS, nRD, nWR go inactive.

STATE 7

nRAS precharge time.

Idle

State 1

State 2

State 3

State 4

State 5

State 6

State 7

PPC34C60 Datasheet(PDF) 31 Page - SMSC Corporation

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