PPC34C60 datasheet(30/58 Pages) SMSC

30 / 58 page

SMSC DS – PPC34C60

Page 30

Rev. 06/01/2001

ADVANCED INFORMATION

5.1 Dram Physical Addressing

Users access the PPC34C60 DRAM through the Host and DMA logical addressing controls found in the Internal Registers.

The system automatically calculates the physical DRAM addresses based on the values stored in these registers and the

width of the system data paths.

The logical addressing controls are the 4-bit encoded Host and DMA DRAM buffer size controls in the DRAM Buffer Size

DRAM Buffer Pointer Register (0111h). The DRAM Data Bus width is determined by RAMSZ0 and RAMSZ1, bits 2 and

3, in the Configuration Register (1100h). The System DMA Data Bus width is determined by D16, bit 1 in the Operation

The PPC34C60 determines physical DRAM addresses by calculating the buffer start address and adjusting this value for

bus width. The buffer start address is the buffer pointer multiplied by the buffer size. If the DRAM Bus width is greater than

or equal to the System Bus width then the buffer start address is the physical DRAM address, otherwise the physical DRAM

address is the buffer start address multiplied by the System Bus width divided by the DRAM Bus width as shown in the

FIGURE 6 below.

FIGURE 6 - DRAM PHYSICAL ADDRESSING

HOST/DMA Bus Width Greater Than DRAM Bus Width

Physical Address = Buffer Ptr * Buffer Size * System Bus Width / DRAM Bus Width

HOST/DMA Bus Width Less Than or Equal to DRAM Bus Width

Physical Address = Buffer Ptr * Buffer Size

For example, during a DMA transfer where;

1. the DRAM data bus width is four bits,

2. the DMA device data bus width is sixteen bits,

3. the DMA Buffer Size is 4096 bytes (1000h),

4. the DRAM Buffer Pointer is 2,

the Physical DRAM Address for the start of this transfer will be 32768 (8000h)

PPC34C60 Datasheet(PDF) 30 Page - SMSC Corporation