PPC34C60 datasheet(26/58 Pages) SMSC

26 / 58 page

SMSC DS – PPC34C60

Page 26

Rev. 06/01/2001

ADVANCED INFORMATION

CONFIGURATION REGISTER - 1100 (Read/Write)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RST

MAXCNT

SFIFO

rsvrd

RAMSZ1

RAMSZ0

CKSEL1

CKSEL0

The bits in this register define the configuration of the system.

Bit 7:RST

Setting this bit resets the storage elements in the chip.

Bit 6:MAXCNT

When this bit is set, the Max Block Count Registers are used to limit the bus and DRAM accesses.

Bit 5:SFIFO

This bit selects the operating mode of the Read FIFO. Setting this bit causes the internal Read FIFO to operate as a single-

word read-ahead. If this bit is clear, the Read FIFO will operate as a two-word read-ahead.

Bit 4:rsvrd

This bit is reserved and should be written as zeros.

Bits[3:2]:RAMSZ[1:0]

RAMSZ1

RAMSZ0

DRAM BUS WIDTH

Selects DRAM data width of 4 bits.

Selects DRAM data width of 8 bits.

Selects DRAM data width of 16 bits.

Bits[1:0]:CKSEL[1:0]

CKSEL1

CKSEL0

BUS CYCLE (BUSCLK)

Bus Cycle (BUSCLK) = System Clock / 2

Bus Cycle (BUSCLK) = System Clock / 3

Bus Cycle (BUSCLK) = System Clock / 5

Bus Cycle (BUSCLK) = System Clock / 6

BUSCLK clocks the Bus Interface State Machine responsible for generating Bus Access, DRAM access, and DRAM

Refresh timing. BUSCLK is also responsible for Output Strobe timing. System Clock is the SCLK input (pin 96) and is

typically 24MHz.

PPC34C60 Datasheet(PDF) 26 Page - SMSC Corporation

PPC34C60 Datasheet(HTML) 26 Page - SMSC Corporation

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