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PPC34C60 Datasheet(PDF) 55 Page - SMSC Corporation

Part # PPC34C60
Description  PARALLEL PORT INTERFACE CHIP PERIPHERAL SIDE
PDF  58 Pages
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Manufacturer  SMSC [SMSC Corporation]
Direct Link  http://www.smsc.com
Logo SMSC - SMSC Corporation

PPC34C60 Datasheet(HTML) 55 Page - SMSC Corporation

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SMSC DS – PPC34C60
Page 55
Rev. 06/01/2001
ADVANCED INFORMATION
FIGURE 25 - DRAM WRITE REFRESH CYCLE
PARAMETER
MIN
TYP
MAX
UNITS
t1
nCAS asserted to nRAS asserted.
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1BCLK
+10]
ns
t2
nCAS asserted pulse width
242
[3 BCLK
-10]
252
[3 BCLK]
262
[3 BCLK
+10]
ns
t3
nRAS asserted pulse width
158
[2 BCLK
-10]
168
[2 BCLK]
178
[2 BCLK
+10]
ns
t4
nCAS deasserted pulse width
74
[1 BCLK
-10]
84
[1 BCLK]
94
[1 BCLK
+10]
ns
t5
nRAS deasserted pulse width
158
[2 BCLK
-10]
168
[2 BCLK]
178
[2 BCLK
+10]
ns
t2
t4
t2
t1
t3
t1
t5
t3
MA[8:9]
SA[0:7]
nCAS
nRAS
HD[0:7]
BUSCLK



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