PPC34C60 datasheet(51/58 Pages) SMSC

51 / 58 page

SMSC DS – PPC34C60

Page 51

Rev. 06/01/2001

ADVANCED INFORMATION

FIGURE 21 - PERIPHERAL BUS READ CYCLE TIMING

PARAMETER

MIN

TYP

MAX

UNITS

nCS asserted to nWR asserted. This applies to any and

all of the general purpose output pins that have been

configured to operate as "special function" Chip Select

pins. This feature saves the designer from having to

implement costly address decoders.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

nIO16 setup required to the assertion of nRD.

nIO16 hold time required from the assertion of nRD.

nRD asserted pulse width.

158

[2 BCLK

- 10]

168

[2 BCLK]

178

[2 BCLK

+10]

Data valid setup time required to deassertion of nRD.

Data valid hold time required from deassertion of nRD.

nRD deasserted to nCS deasserted.

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

nRD deasserted to the address incremented (this is valid

only if the AUTOINC bit is set).

[1 BCLK

-10]

[1 BCLK]

[1BCLK

+10]

valid

Data Valid

Address Valid

Address+1

AUTOINC bit set

nCAS

nRAS

nCS

nIO16

nRD

nWR

SD[0:15]

SA[0:7]

BUSCLK

PPC34C60 Datasheet(PDF) 51 Page - SMSC Corporation

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