PPC34C60 datasheet(45/58 Pages) SMSC

45 / 58 page

SMSC DS – PPC34C60

Page 45

Rev. 06/01/2001

ADVANCED INFORMATION

FIGURE 16 - EPP DATA WRITE TIMING (PARALLEL PORT SIGNALS)

See EPP Data Write Timing parameters.

EPP DATA WRITE TIMING (PARALLEL PORT SIGNALS)

PARAMETER

MIN

TYP

MAX

UNITS

The Host asserts nSTB to indicate that the

forthcoming transfer is a write cycle. At the

same time or soon after the Host places

the address byte on HD[0:7].

This

specifies the time between nSTB being

asserted and an address appearing on

HD[0:7]. The PPC34C60 does not rely on

nSTB.

After placing an address on HD[0:7], the

Host then asserts nALF to inform the

PPC34C60 that a data cycle is taking

place.

The PPC34C60 will detect the assertion of

nALF and will assert BSY to indicate that it

has latched the data on HD[0:7].

250

[6 SCLK]

10,000

After the PPC34C60 asserts BSY the Host

will then indicate that the cycle is complete

by deasserting nALF. This represents the

response time requirements put on the

Host.

[SCLK]

Seeing that the Host has indicated that the

cycle is complete, the PPC34C60 will then

deassert the BSY line as soon as it is ready

for another EPP transfer.

209

[5 SCLK]

As soon as the PPC34C60 deasserts BSY

the Host may initiate another EPP transfer.

This time represents the time between the

PPC34C60 deasserting BSY to the Host

starting a new transfer cycle.

VALID DATA

HD[0:7]

nSTB H

nALF H

nSEL H

nINIT H

BSY P

nACK P

PE P

SLCT P

nERR P

PPC34C60 Datasheet(PDF) 45 Page - SMSC Corporation

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