TMS320VC5416 datasheet(46/98 Pages) TI1

46 / 98 page

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

www.ti.com

Table 3-16. Peripheral Memory-Mapped Registers for Each DSP Subsystem (continued)

ADDRESS

NAME

DESCRIPTION

DEC

HEX

—

Reserved

SWWSR

Software Wait-State Register

BSCR

Bank-Switching Control Register

—

Reserved

SWCR

Software Wait-State Control Register

HPIC

HPI Control Register (HMODE = 0 only)

—

45-47

2D-2F

Reserved

DRR22

McBSP 2 Data Receive Register 2

DRR12

McBSP 2 Data Receive Register 1

DXR22

McBSP 2 Data Transmit Register 2

DXR12

McBSP 2 Data Transmit Register 1

SPSA2

McBSP 2 Subbank Address Register(1)

SPSD2

McBSP 2 Subbank Data Register(1)

—

54-55

36-37

Reserved

SPSA0

McBSP 0 Subbank Address Register(1)

SPSD0

McBSP 0 Subbank Data Register(1)

—

58-59

3A-3B

Reserved

GPIOCR

General-Purpose I/O Control Register

GPIOSR

General-Purpose I/O Status Register

CSIDR

Device ID Register

—

Reserved

DRR21

McBSP 1 Data Receive Register 2

DRR11

McBSP 1 Data Receive Register 1

DXR21

McBSP 1 Data Transmit Register 2

DXR11

McBSP 1 Data Transmit Register 1

—

68-71

44-47

Reserved

SPSA1

McBSP 1 Subbank Address Register(1)

SPSD1

McBSP 1 Subbank Data Register(1)

—

74-83

4A-53

Reserved

DMPREC

DMA Priority and Enable Control Register

DMSA

DMA Subbank Address Register(2)

DMSDI

DMA Subbank Data Register with Autoincrement(2)

DMSDN

DMA Subbank Data Register(2)

CLKMD

Clock Mode Register (CLKMD)

—

89-95

59-5F

Reserved

(1)

See Table 3-17 for a detailed description of the McBSP control registers and their subaddresses.

(2)

See Table 3-18 for a detailed description of the DMA subbank addressed registers.

Functional Overview

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