TMS320VC5416 datasheet(63/98 Pages) TI1

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5.5.2

Memory Write

tsu(D)MSH

td(CLKL-MSH)

td(CLKL-A)

CLKOUT

A[22:0]

(see Note A)

D[15:0]

MSTRB

R/W

(see Note A)

PS/DS

(see Note A)

td(CLKL-D)W

td(CLKL-MSL)

tsu(A)MSL

th(D)MSH

tw(SL)MS

td(CLKL-A)

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

Table 5-9 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see

Figure 5-7).

Table 5-9. Memory Write Switching Characteristics

5416-120

5416-160

PARAMETER

UNIT

MIN

MAX

td(CLKL-A)

Delay time, CLKOUT low to address valid(1)

–1

tsu(A)MSL

Setup time, address valid before MSTRB low(1)

2H – 3

td(CLKL-D)W

Delay time, CLKOUT low to data valid

–1

tsu(D)MSH

Setup time, data valid before MSTRB high

2H – 4

2H + 6

th(D)MSH

Hold time, data valid after MSTRB high

2H – 5

2H + 6

td(CLKL-MSL)

Delay time, CLKOUT low to MSTRB low

–1

tw(SL)MS

Pulse duration, MSTRB low

2H – 2

td(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high

(1)

Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.

Figure 5-7. Memory Write (MSTRB = 0)

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