TMS320VC5416 datasheet(64/98 Pages) TI1

64 / 98 page

5.5.3

I/O Read

td(CLKL-IOSH)

th(D)R

td(CLKL-A)

CLKOUT

A[22:0]

(see Note A)

D[15:0]

IOSTRB

R/W

(see Note A)

td(CLKL-IOSL)

tsu(D)R

ta(A)M1

td(CLKL-A)

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

www.ti.com

Table 5-10 and Table 5-11 assume testing over recommended operating conditions, IOSTRB = 0, and

H = 0.5tc(CO) (see Figure 5-8).

Table 5-10. I/O Read Timing Requirements

5416-120

5416-160

UNIT

MIN

MAX

ta(A)M1

Access time, read data access from address valid, first read access(1)

4H – 9

tsu(D)R

Setup time, read data valid before CLKOUT low

th(D)R

Hold time, read data valid after CLKOUT low

(1)

Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.

Table 5-11. I/O Read Switching Characteristics

5416-120

5416-160

PARAMETER

UNIT

MIN

MAX

td(CLKL-A)

Delay time, CLKOUT low to address valid(1)

– 1

td(CLKL-IOSL)

Delay time, CLKOUT low to IOSTRB low

– 1

td(CLKL-IOSH)

Delay time, CLKOUT low to IOSTRB high

(1)

Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.

Figure 5-8. Parallel I/O Port Read (IOSTRB = 0)

Electrical Specifications

Submit Documentation Feedback

TMS320VC5416 Datasheet(PDF) 64 Page - Texas Instruments

TMS320VC5416 Datasheet(HTML) 64 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Download

Link URL