TMS320VC5416 datasheet(75/98 Pages) TI1

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5.5.8 Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings

IACK

IAQ

A[22:0]

CLKOUT

td(CLKL−A)

tw(IACKL)

td(CLKL−IACKL)

tw(IAQL)

td(CLKL−IAQL)

td(CLKL−IACKH)

td(CLKL−IAQH)

td(CLKL−A)

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

Table 5-18 assumes testing over recommended operating conditions and H = 0.5tc(CO) (see Figure 5-18).

Table 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Switching Characteristics

5416-120

5416-160

PARAMETER

UNIT

MIN

MAX

td(CLKL-IAQL)

Delay time, CLKOUT low to IAQ low

– 1

td(CLKL-IAQH)

Delay time, CLKOUT low to IAQ high

– 1

td(CLKL-IACKL)

Delay time, CLKOUT low to IACK low

– 1

td(CLKL-IACKH)

Delay time, CLKOUT low to IACK high

– 1

td(CLKL-A)

Delay time, CLKOUT low to address valid

– 1

tw(IAQL)

Pulse duration, IAQ low

2H – 2

tw(IACKL)

Pulse duration, IACK low

2H – 2

Figure 5-18. Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings

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