L6751C datasheet(19/57 Pages) STMICROELECTRONICS

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L6751C

Device configuration and pin-strapping tables

The L6751C device features a universal serial data bus fully compliant with Intel

VR12/IMVP7 Protocol rev 1.5, document #456098 and AMD SVI specifications, document

#40182. To guarantee proper device and CPU operation, refer to these documents for bus

design, layout guidelines and any additional information required for the bus architecture.

Different platforms may require different pull-up impedance on the SVI bus. Impedance

matching and spacing among SVI bus lines must be followed.

The controller configures itself automatically upon detection of different pin-strappings which

are monitored at the IC power-up. See Table 6, 8, 9, Table 10 on page 23, and Table 11 on

page 24 for details.

4.1

JMode

When enabled, multi-phase acts as if in DDR mode, while single-phase is an independent

regulator with 0.75 V fixed reference (load-line disabled - TM can be used as enable for the

single-phase).

Output voltage higher than the internal reference may be achieved by adding a proper

resistor divider (RA, RB - see Figure 4). To maintain precision in output voltage regulation, it

is recommended to provide both SFBR and SRGND with the same divider.

Equation 1

Figure 4. JMode: voltage positioning

VOUT

0.750

RA RB

---------------------



0.750V

SFB

SCOMP

SVSEN

SFBR

RFB

To Vout

(Remote Sense)

SRGND

AM14812v1

L6751C Datasheet(PDF) 19 Page - STMicroelectronics